Move target definition into individual files.
[riscv-tests.git] / debug / targets / SiFive / Freedom / E300Sim.py
1 import targets
2
3 class E300Sim(targets.Target):
4 xlen = 32
5 timeout_sec = 6000
6 ram = 0x80000000
7 ram_size = 256 * 1024 * 1024
8 instruction_hardware_breakpoint_count = 2
9 openocd_config_path = "Freedom.cfg"
10 link_script_path = "Freedom.lds"
11
12 def target(self):
13 return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)