Give these sim targets a chance of passing.
[riscv-tests.git] / debug / targets / SiFive / Freedom / E300Sim.py
1 import targets
2 import testlib
3
4 class E300Sim(targets.Target):
5 xlen = 32
6 timeout_sec = 6000
7 ram = 0x80000000
8 ram_size = 256 * 1024 * 1024
9 instruction_hardware_breakpoint_count = 2
10 openocd_config_path = "Freedom.cfg"
11 link_script_path = "Freedom.lds"
12
13 def create(self):
14 return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)