isa/rv64si/csr.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # csr.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test CSRRx and CSRRxI instructions.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16 #ifdef __MACHINE_MODE
  17   #define sscratch mscratch
  18   #define sstatus mstatus
  19   #define scause mcause
  20   #define sepc mepc
  21   #define sret mret
  22   #define stvec_handler mtvec_handler
  23   #undef SSTATUS_SPP
  24   #define SSTATUS_SPP MSTATUS_MPP
  25 #endif
  26
  27   # For RV64, make sure UXL encodes RV64.  (UXL does not exist for RV32.)
  28 #if __riscv_xlen == 64
  29   TEST_CASE(13, a0, SSTATUS_UXL & (SSTATUS_UXL << 1), csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1)
  30 #endif
  31
  32   csrwi sscratch, 3
  33   TEST_CASE( 2, a0,         3, csrr a0, sscratch);
  34   TEST_CASE( 3, a1,         3, csrrci a1, sscratch, 1);
  35   TEST_CASE( 4, a2,         2, csrrsi a2, sscratch, 4);
  36   TEST_CASE( 5, a3,         6, csrrwi a3, sscratch, 2);
  37   TEST_CASE( 6, a1,         2, li a0, 0xbad1dea; csrrw a1, sscratch, a0);
  38   TEST_CASE( 7, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sscratch, a0);
  39   TEST_CASE( 8, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0);
  40   TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch);
  41
  42 #ifdef __MACHINE_MODE
  43   # Is F extension present?
  44   csrr a0, misa
  45   andi a0, a0, (1 << ('F' - 'A'))
  46   beqz a0, 1f
  47   # If so, make sure FP stores have no effect when mstatus.FS is off.
  48   li a1, MSTATUS_FS
  49   csrs mstatus, a1
  50   fmv.s.x f0, x0
  51   csrc mstatus, a1
  52   la a1, fsw_data
  53   TEST_CASE(10, a0, 1, fsw f0, (a1); lw a0, (a1));
  54 1:
  55
  56   # Figure out if 'U' is set in misa
  57   csrr a0, misa   # a0 = csr(misa)
  58   srli a0, a0, 20 # a0 = a0 >> 20
  59   andi a0, a0, 1  # a0 = a0 & 1
  60   beqz a0, finish # if no user mode, skip the rest of these checks
  61 #endif
  62
  63   # jump to user land
  64   li t0, SSTATUS_SPP
  65   csrc sstatus, t0
  66   la t0, 1f
  67   csrw sepc, t0
  68   sret
  69   1:
  70
  71   # Make sure writing the cycle counter causes an exception.
  72   # Don't run in supervisor, as we don't delegate illegal instruction traps.
  73 #ifdef __MACHINE_MODE
  74   TEST_CASE(11, a0, 255, li a0, 255; csrrw a0, cycle, x0);
  75 #endif
  76
  77   # Make sure reading status in user mode causes an exception.
  78   # Don't run in supervisor, as we don't delegate illegal instruction traps.
  79 #ifdef __MACHINE_MODE
  80   TEST_CASE(12, a0, 255, li a0, 255; csrr a0, sstatus)
  81 #else
  82   TEST_CASE(12, x0, 0, nop)
  83 #endif
  84
  85 finish:
  86   RVTEST_PASS
  87
  88   # We should only fall through to this if scall failed.
  89   TEST_PASSFAIL
  90
  91   .align 2
  92 stvec_handler:
  93   # Trapping on tests 10-12 is good news.
  94   # Note that since the test didn't complete, TESTNUM is smaller by 1.
  95   li t0, 9
  96   bltu TESTNUM, t0, 1f
  97   li t0, 11
  98   bleu TESTNUM, t0, privileged
  99 1:
 100
 101   # catch RVTEST_PASS and kick it up to M-mode
 102   csrr t0, scause
 103   li t1, CAUSE_USER_ECALL
 104   bne t0, t1, fail
 105   RVTEST_PASS
 106
 107 privileged:
 108   # Make sure scause indicates a lack of privilege.
 109   csrr t0, scause
 110   li t1, CAUSE_ILLEGAL_INSTRUCTION
 111   bne t0, t1, fail
 112   # Return to user mode, but skip the trapping instruction.
 113   csrr t0, sepc
 114   addi t0, t0, 4
 115   csrw sepc, t0
 116   sret
 117
 118 RVTEST_CODE_END
 119
 120   .data
 121 RVTEST_DATA_BEGIN
 122
 123 fsw_data: .word 1
 124
 125 RVTEST_DATA_END