isa/rv64si/csr.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # csr.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test CSRRx and CSRRxI instructions.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16 #ifdef __MACHINE_MODE
  17   #define sscratch mscratch
  18   #define sstatus mstatus
  19   #define scause mcause
  20   #define sepc mepc
  21   #define sret mret
  22   #define stvec_handler mtvec_handler
  23   #undef SSTATUS_SPP
  24   #define SSTATUS_SPP MSTATUS_MPP
  25 #endif
  26
  27   # For RV64, make sure UXL encodes RV64.  (UXL does not exist for RV32.)
  28 #if __riscv_xlen == 64
  29   TEST_CASE(13, a0, SSTATUS_UXL & (SSTATUS_UXL << 1), csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1)
  30 #endif
  31
  32   csrwi sscratch, 3
  33   TEST_CASE( 2, a0,         3, csrr a0, sscratch);
  34   TEST_CASE( 3, a1,         3, csrrci a1, sscratch, 1);
  35   TEST_CASE( 4, a2,         2, csrrsi a2, sscratch, 4);
  36   TEST_CASE( 5, a3,         6, csrrwi a3, sscratch, 2);
  37   TEST_CASE( 6, a1,         2, li a0, 0xbad1dea; csrrw a1, sscratch, a0);
  38   TEST_CASE( 7, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sscratch, a0);
  39   TEST_CASE( 8, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0);
  40   TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch);
  41
  42 #ifdef __MACHINE_MODE
  43   # Is F extension present?
  44   csrr a0, misa
  45   andi a0, a0, (1 << ('F' - 'A'))
  46   beqz a0, 1f
  47   # If so, make sure FP stores have no effect when mstatus.FS is off.
  48   li a1, MSTATUS_FS
  49   csrs mstatus, a1
  50 #ifdef __riscv_flen
  51   fmv.s.x f0, x0
  52   csrc mstatus, a1
  53   la a1, fsw_data
  54   TEST_CASE(10, a0, 1, fsw f0, (a1); lw a0, (a1));
  55 #else
  56   # Fail if this test is compiled without F but executed on a core with F.
  57   TEST_CASE(10, zero, 1)
  58 #endif
  59 1:
  60
  61   # Figure out if 'U' is set in misa
  62   csrr a0, misa   # a0 = csr(misa)
  63   srli a0, a0, 20 # a0 = a0 >> 20
  64   andi a0, a0, 1  # a0 = a0 & 1
  65   beqz a0, finish # if no user mode, skip the rest of these checks
  66 #endif /* __MACHINE_MODE */
  67
  68   # jump to user land
  69   li t0, SSTATUS_SPP
  70   csrc sstatus, t0
  71   la t0, 1f
  72   csrw sepc, t0
  73   sret
  74   1:
  75
  76   # Make sure writing the cycle counter causes an exception.
  77   # Don't run in supervisor, as we don't delegate illegal instruction traps.
  78 #ifdef __MACHINE_MODE
  79   TEST_CASE(11, a0, 255, li a0, 255; csrrw a0, cycle, x0);
  80 #endif
  81
  82   # Make sure reading status in user mode causes an exception.
  83   # Don't run in supervisor, as we don't delegate illegal instruction traps.
  84 #ifdef __MACHINE_MODE
  85   TEST_CASE(12, a0, 255, li a0, 255; csrr a0, sstatus)
  86 #else
  87   TEST_CASE(12, x0, 0, nop)
  88 #endif
  89
  90 finish:
  91   RVTEST_PASS
  92
  93   # We should only fall through to this if scall failed.
  94   TEST_PASSFAIL
  95
  96   .align 2
  97 stvec_handler:
  98   # Trapping on tests 10-12 is good news.
  99   # Note that since the test didn't complete, TESTNUM is smaller by 1.
 100   li t0, 9
 101   bltu TESTNUM, t0, 1f
 102   li t0, 11
 103   bleu TESTNUM, t0, privileged
 104 1:
 105
 106   # catch RVTEST_PASS and kick it up to M-mode
 107   csrr t0, scause
 108   li t1, CAUSE_USER_ECALL
 109   bne t0, t1, fail
 110   RVTEST_PASS
 111
 112 privileged:
 113   # Make sure scause indicates a lack of privilege.
 114   csrr t0, scause
 115   li t1, CAUSE_ILLEGAL_INSTRUCTION
 116   bne t0, t1, fail
 117   # Return to user mode, but skip the trapping instruction.
 118   csrr t0, sepc
 119   addi t0, t0, 4
 120   csrw sepc, t0
 121   sret
 122
 123 RVTEST_CODE_END
 124
 125   .data
 126 RVTEST_DATA_BEGIN
 127
 128 fsw_data: .word 1
 129
 130 RVTEST_DATA_END