isa/rv64si/ma_fetch.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_fetch.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned fetch trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16 #ifdef __MACHINE_MODE
  17   #define sscratch mscratch
  18   #define sstatus mstatus
  19   #define scause mcause
  20   #define sbadaddr mbadaddr
  21   #define sepc mepc
  22   #define sret mret
  23   #define stvec_handler mtvec_handler
  24 #endif
  25
  26   .align 2
  27   .option norvc
  28
  29   # Without RVC, the jalr should trap, and the handler will skip ahead.
  30   # With RVC, the jalr should not trap, and "j fail" should get skipped.
  31   li TESTNUM, 2
  32   li t1, 0
  33   la t0, 1f
  34   jalr t1, t0, 2
  35 1:
  36   .option rvc
  37   c.j 1f
  38   c.j 2f
  39   .option norvc
  40 1:
  41   j fail
  42 2:
  43
  44   // This test should pass, since JALR ignores the target LSB
  45   li TESTNUM, 3
  46   la t0, 1f
  47   jalr t1, t0, 1
  48 1:
  49   j 1f
  50   j fail
  51 1:
  52
  53   li TESTNUM, 4
  54   li t1, 0
  55   la t0, 1f
  56   jalr t1, t0, 3
  57 1:
  58   .option rvc
  59   c.j 1f
  60   c.j 2f
  61   .option norvc
  62 1:
  63   j fail
  64 2:
  65
  66   # Like test 2, but with jal instead of jalr.
  67   li TESTNUM, 5
  68   li t1, 0
  69   la t0, 1f
  70   jal t1, 2f
  71 1:
  72   .option rvc
  73   c.j 1f
  74 2:
  75   c.j 2f
  76   .option norvc
  77 1:
  78   j fail
  79 2:
  80
  81   # Like test 2, but with a taken branch instead of jalr.
  82   li TESTNUM, 6
  83   li t1, 0
  84   la t0, 1f
  85   beqz x0, 2f
  86 1:
  87   .option rvc
  88   c.j 1f
  89 2:
  90   c.j 2f
  91   .option norvc
  92 1:
  93   j fail
  94 2:
  95
  96   # Not-taken branches should not trap, even without RVC.
  97   li TESTNUM, 7
  98   bnez x0, 1f
  99   j 2f
 100   .option rvc
 101   c.j 1f
 102 1:
 103   c.j 1f
 104   .option norvc
 105 1:
 106   j fail
 107 2:
 108
 109 #ifdef __MACHINE_MODE
 110   # If RVC can be disabled, then disabling it should cause a misaligned
 111   # instruction exception on the next instruction.  (This test assumes
 112   # no other extensions that support misalignment are present.)
 113   li TESTNUM, 8
 114   csrr t2, misa
 115   andi t2, t2, 1 << ('c' - 'a')
 116   beqz t2, 2f
 117
 118   la t0, 1f
 119   .option rvc
 120   c.nop
 121   csrci misa, 1 << ('c' - 'a')
 122 1:
 123   c.j 1f
 124   .option norvc
 125
 126   # If we got here, we trapped.  Re-enable RVC and proceed.
 127   csrsi misa, 1 << ('c' - 'a')
 128   j 2f
 129
 130 1:
 131   # If we got here, we didn't trap, so RVC had better be enabled.
 132   csrr t2, misa
 133   andi t2, t2, 1 << ('c' - 'a')
 134   beqz t2, fail
 135
 136 2:
 137   # mret to a misaligned mepc should either align the mepc or raise a
 138   # misaligned instruction exception.
 139   la t0, 1f
 140   addi t0, t0, -2
 141   csrw mepc, t0
 142
 143   # Try to disable RVC; if it can't be disabled, skip the test.
 144   csrci misa, 1 << ('c' - 'a')
 145   csrr t2, misa
 146   andi t2, t2, 1 << ('c' - 'a')
 147   bnez t2, 2f
 148
 149   li t2, MSTATUS_MPP
 150   csrs mstatus, t2
 151   mret
 152
 153   # If the implementation chose to align mepc, mret will transfer control
 154   # to this branch.  Otherwise, it will transfer control two bytes into
 155   # the branch, which happens to be the illegal instruction c.unimp.
 156   # But c.unimp should not be executed, since the PC is misaligned.
 157   beqz x0, 1f
 158 1:
 159   j 2f
 160
 161 test8_handler:
 162   # verify trap cause
 163   li a1, CAUSE_MISALIGNED_FETCH
 164   csrr a0, mcause
 165   bne a0, a1, fail
 166
 167   # check that mepc == t0, and advance mepc past the misalignment
 168   csrr a0, mepc
 169   bne a0, t0, fail
 170   addi a0, a0, 2
 171   csrw mepc, a0
 172
 173   # check that badaddr == t0 or zero
 174   csrr a0, mbadaddr
 175   beqz a0, 1f
 176   bne a0, t0, fail
 177 1:
 178   mret
 179
 180 2:
 181 #endif
 182
 183   j pass
 184
 185   TEST_PASSFAIL
 186
 187   .align 2
 188   .global stvec_handler
 189 stvec_handler:
 190   # tests 2, 4, 5, 6, and 8 should trap
 191   li a0, 2
 192   beq TESTNUM, a0, 1f
 193   li a0, 4
 194   beq TESTNUM, a0, 1f
 195   li a0, 5
 196   beq TESTNUM, a0, 1f
 197   li a0, 6
 198   beq TESTNUM, a0, 1f
 199 #ifdef __MACHINE_MODE
 200   li a0, 8
 201   beq TESTNUM, a0, test8_handler
 202 #endif
 203   j fail
 204 1:
 205
 206   # verify that return address was not written
 207   bnez t1, fail
 208
 209   # verify trap cause
 210   li a1, CAUSE_MISALIGNED_FETCH
 211   csrr a0, scause
 212   bne a0, a1, fail
 213
 214   # verify that epc == &jalr (== t0 - 4)
 215   csrr a1, sepc
 216   addi a1, a1, 4
 217   bne t0, a1, fail
 218
 219   # verify that badaddr == 0 or badaddr == t0+2.
 220   csrr a0, sbadaddr
 221   beqz a0, 1f
 222   addi a0, a0, -2
 223   bne a0, t0, fail
 224 1:
 225
 226   addi a1, a1, 12
 227   csrw sepc, a1
 228   sret
 229
 230 RVTEST_CODE_END
 231
 232   .data
 233 RVTEST_DATA_BEGIN
 234
 235   TEST_DATA
 236
 237 RVTEST_DATA_END