Remove instruction width assumptions to support RVC
[riscv-tests.git] / isa / rv64si / ma_fetch.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # ma_fetch.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test misaligned fetch trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64S
14 RVTEST_CODE_BEGIN
15
16 #ifdef __MACHINE_MODE
17 #define sscratch mscratch
18 #define sstatus mstatus
19 #define scause mcause
20 #define sepc mepc
21 #define sret mret
22 #define stvec_handler mtvec_handler
23 #endif
24
25 .option norvc
26
27 # Without RVC, the jalr should trap, and the handler will skip ahead.
28 # With RVC, the jalr should not trap, and "j fail" should get skipped.
29 li TESTNUM, 2
30 li t1, 0
31 la t0, 1f
32 jalr t1, t0, 2
33 1:
34 .option rvc
35 c.j fail
36 c.j 2f
37 .option norvc
38 j fail
39 2:
40
41 // This test should pass, since JALR ignores the target LSB
42 li TESTNUM, 3
43 la t0, 1f
44 jalr t1, t0, 1
45 1:
46 j 1f
47 j fail
48 1:
49
50 li TESTNUM, 4
51 li t1, 0
52 la t0, 1f
53 jalr t1, t0, 3
54 1:
55 .option rvc
56 c.j fail
57 c.j 2f
58 .option norvc
59 j fail
60 2:
61
62 j pass
63
64 TEST_PASSFAIL
65
66 .align 2
67 stvec_handler:
68 # tests 2 and 4 should trap
69 li a0, 2
70 beq TESTNUM, a0, 1f
71 li a0, 4
72 beq TESTNUM, a0, 1f
73 j fail
74 1:
75
76 # verify that return address was not written
77 bnez t1, fail
78
79 # verify trap cause
80 li a1, CAUSE_MISALIGNED_FETCH
81 csrr a0, scause
82 bne a0, a1, fail
83
84 # verify that epc == &jalr (== t0 - 4)
85 csrr a1, sepc
86 addi t0, t0, -4
87 bne t0, a1, fail
88
89 addi a1, a1, 12
90 csrw sepc, a1
91 sret
92
93 RVTEST_CODE_END
94
95 .data
96 RVTEST_DATA_BEGIN
97
98 TEST_DATA
99
100 RVTEST_DATA_END