Merge pull request #52 from riscv/vcs_sim_cmd
authorMegan Wachs <megan@sifive.com>
Thu, 18 May 2017 19:14:07 +0000 (12:14 -0700)
committerGitHub <noreply@github.com>
Thu, 18 May 2017 19:14:07 +0000 (12:14 -0700)
commit5ff7b723976b3736daa0f0ad5df71d40576a674a
tree9a356049eecc480d8910c75f56b1a8db06a8538e
parent019192fead976af698d16b090d75be2dc7da053e
parentd74b266e4fa780ec0b42663b752deaa58fda91ae
Merge pull request #52 from riscv/vcs_sim_cmd

debug: Correct the calling for a 32-bit simulation target