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[shakti-peripherals.git] / src / peripherals / flexbus / FlexBus_Types.bsv
1 // Copyright (c) 2017 Bluespec, Inc. All Rights Reserved
2
3 package FlexBus_Types;
4
5 // ================================================================
6 // See export list below
7 // ================================================================
8 // Exports
9
10 export
11
12 // RTL-level interfaces (signals/buses)
13 FlexBus_Slave_IFC (..),
14 FlexBus_Master_IFC (..),
15
16
17 // Higher-level enums and structs for the FlexBus
18 FlexBus_States (..),
19
20 FlexBus_Payload (..),
21 FlexBus_Attr (..),
22 FlexBus_din (..),
23 FlexBus_Signals (..),
24
25 // Higher-level FIFO-like interfaces for the 5 AXI4 channels,
26 FlexBus_Register_IFC (..),
27 FlexBus_Register_Output_IFC (..),
28 FlexBus_Register_Input_IFC (..),
29
30 AXI4_Slave_to_FlexBus_Master_Xactor_IFC (..),
31
32 // Transactors from RTL-level interfacecs to FIFO-like interfaces.
33 mkAXI4_Slave_to_FlexBus_Master_Xactor;
34
35 // ================================================================
36 // BSV library imports
37
38 import Vector :: *;
39 import FIFOF :: *;
40 import GetPut :: *;
41 import SpecialFIFOs:: *;
42 import Connectable :: *;
43 import ConfigReg :: *;
44 `include "instance_defines.bsv"
45
46 // ----------------
47 // BSV additional libs
48
49 import Semi_FIFOF :: *;
50 import AXI4_Types :: *;
51
52 //import Memory_AXI4 :: *;
53
54 // ****************************************************************
55 // ****************************************************************
56 // Section: RTL-level interfaces
57 // ****************************************************************
58 // ****************************************************************
59
60 // ================================================================
61 // These are the signal-level interfaces for an FlexBus master.
62 // The (*..*) attributes ensure that when bsc compiles this to Verilog,
63 // we get exactly the signals specified in the FlexBus spec.
64
65 (* always_ready *)
66 interface FlexBus_Master_IFC;
67 // FlexBus External Signals
68
69 // AD inout bus separate for now in BSV
70 interface Get#(Bit#(32)) m_AD; // out
71 interface Put#(Bit#(32)) m_din; // in
72 interface Get#(Bit#(32)) m_OE32n; // out 32-bits, same as OEn
73
74 interface Get#(Bit#(1)) m_R_Wn; // out
75 interface Get#(Bit#(2)) m_TSIZ; // out
76
77 interface Get#(Bit#(6)) m_FBCSn; // out
78 interface Get#(Bit#(4)) m_BWEn; // out
79 interface Get#(Bit#(1)) m_TBSTn; // out
80 interface Get#(Bit#(1)) m_OEn; // out
81
82 interface Get#(Bit#(1)) m_ALE; // out
83 interface Put#(Bit#(1)) m_tAn; // in
84
85 endinterface: FlexBus_Master_IFC
86
87 interface FlexBus_Register_Input_IFC;
88 method Action reset (Bit#(32) ad_bus);
89 method Action m_ad_bus (Bit#(32) ad_bus);
90 method Action m_data_bus (Bit#(32) data_bus);
91 endinterface: FlexBus_Register_Input_IFC
92
93 interface FlexBus_Register_Output_IFC;
94 (* always_ready, always_enabled *) method Bit#(6) m_FBCSn();
95 (* always_ready, always_enabled *) method Bit#(6) m_SWS();
96 (* always_ready, always_enabled *) method Bit#(1) m_SWS_EN();
97 (* always_ready, always_enabled *) method Bit#(2) m_ASET();
98 (* always_ready, always_enabled *) method Bit#(2) m_RDAH();
99 (* always_ready, always_enabled *) method Bit#(2) m_WRAH();
100 (* always_ready, always_enabled *) method Bit#(6) m_WS();
101 (* always_ready, always_enabled *) method Bit#(1) m_AA();
102 (* always_ready, always_enabled *) method Bit#(2) m_PS();
103 (* always_ready, always_enabled *) method Bit#(1) m_BEM();
104 (* always_ready, always_enabled *) method Bit#(1) m_BSTR();
105 (* always_ready, always_enabled *) method Bit#(1) m_BSTW();
106 endinterface: FlexBus_Register_Output_IFC
107
108 interface FlexBus_Register_IFC;
109 interface FlexBus_Register_Input_IFC inp_side;
110 interface FlexBus_Register_Output_IFC op_side;
111 endinterface: FlexBus_Register_IFC
112
113 // ================================================================
114 // These are the signal-level interfaces for an AXI4-Lite slave.
115 // The (*..*) attributes ensure that when bsc compiles this to Verilog,
116 // we get exactly the signals specified in the ARM spec.
117 interface FlexBus_Slave_IFC ;
118
119 /*
120 (* result="AD" *) interface Put#(Bit#(32)) m_AD; // out
121 interface Get#(Bit#(32) m_din; // in
122
123 (* result="R_Wn" *) interface Put#(Bit#(1)) m_R_Wn; // out
124 (* result="TSIZ" *) interface Put#(Bit #(2) m_TSIZ; // out
125
126 (* result="FBCSn" *) interface Put#(Bit#(6)) m_FBCSn; // out
127 (* result="BEn_BWEn" *) interface Put#(Bit#(4)) m_BE_BWEn; // out
128 (* result="TBSTn" *) interface Put#(Bit#(1)) m_TBSTn; // out
129 (* result="OEn" *) interface Put#(Bit#(1)) m_OEn; // out
130
131 (* result="ALE" *) interface Put#(Bit#(1)) m_ALE; // out
132 interface Get#(Bit#(1) tAn; // in
133 */
134
135 (* always_ready, always_enabled *)
136 method Action m_AD ( (* port="AD" *) Bit #(32) i_AD); // in
137
138
139 (* always_ready, always_enabled *)
140 method Action m_ALE ( (* port="ALE" *) Bit #(1) i_ALE); // in
141
142 (* always_ready, always_enabled *)
143 method Action m_R_Wn ( (* port="R_Wn" *) Bit #(1) i_R_Wn); // in
144 (* always_ready, always_enabled *)
145 method Action m_TSIZ ( (* port="TSIZ" *) Bit #(2) i_TSIZ); // in
146
147 (* always_ready, always_enabled *)
148 method Action m_FBCSn ( (* port="FBCSn" *) Bit #(6) i_FBCSn); // in
149 (* always_ready, always_enabled *)
150 method Action m_BE_BWEn( (* port="BE_BWEn" *) Bit #(4) i_BE_BWEn); // in
151 (* always_ready, always_enabled *)
152 method Action m_TBSTn ( (* port="TBSTn" *) Bit #(1) i_TBSTn); // in
153 (* always_ready, always_enabled *)
154 method Action m_OEn ( (* port="OEn" *) Bit #(1) i_OEn); // in
155
156 (* always_ready, result="din" *)
157 method Bit #(32) m_din; // out
158 (* always_ready, result="TAn" *)
159 method Bit #(1) m_TAn; // out
160
161 endinterface: FlexBus_Slave_IFC
162
163
164 // ================================================================
165 // Connecting signal-level interfaces
166
167 `ifdef DISABLED_FOR_NOW // TODO. convert to get/put including slave ifc
168 instance Connectable #(FlexBus_Master_IFC ,
169 FlexBus_Slave_IFC );
170
171 module mkConnection #(FlexBus_Master_IFC flexbus_m,
172 FlexBus_Slave_IFC flexbus_s)
173 (Empty);
174
175 (* fire_when_enabled, no_implicit_conditions *)
176 rule rl_flexbus_AD_signals;
177 flexbus_s.m_AD (flexbus_m.m_AD);
178 endrule
179
180
181 (* fire_when_enabled, no_implicit_conditions *)
182 rule rl_flexbus_Attr_signals;
183 flexbus_s.m_ALE (flexbus_m.m_ALE);
184 flexbus_s.m_R_Wn (flexbus_m.m_R_Wn);
185 flexbus_s.m_TSIZ (flexbus_m.m_TSIZ);
186 endrule
187 (* fire_when_enabled, no_implicit_conditions *)
188 rule rl_flexbus_signals;
189 flexbus_s.m_FBCSn (flexbus_m.m_FBCSn);
190 flexbus_s.m_BE_BWEn (flexbus_m.m_BE_BWEn);
191 flexbus_s.m_TBSTn (flexbus_m.m_TBSTn);
192 flexbus_s.m_OEn (flexbus_m.m_OEn);
193 endrule
194 (* fire_when_enabled *)
195 //(* fire_when_enabled, no_implicit_conditions *)
196 rule rl_flexbus_input_signals;
197 flexbus_m.m_din (flexbus_s.m_din);
198 flexbus_m.m_TAn (flexbus_s.m_TAn);
199 endrule
200
201 endmodule
202 endinstance
203 `endif
204
205 // ****************************************************************
206 // ****************************************************************
207 // Section: Higher-level FIFO-like interfaces and transactors
208 // ****************************************************************
209 // ****************************************************************
210
211 // ================================================================
212 // Higher-level types for payloads (rather than just bits)
213
214 typedef enum { IDLE, FlexBus_S0_DEQ_WR_FIFOS, FlexBus_S0_DEQ_RD_FIFOS, FlexBus_S1_ADDR, FlexBus_S2_WRITE, FlexBus_S3_BURST, FlexBus_S4_HOLD } FlexBus_States deriving (Bits, Eq, FShow);
215 typedef enum { IDLE, FlexBus_S0_CHK_FIFOS, FlexBus_S0_DEQ_FIFOS, FlexBus_WRITE_DUMMY1, FlexBus_WRITE_DUMMY2 } FlexBus_States_wr deriving (Bits, Eq, FShow);
216 typedef enum { IDLE, FlexBus_S0_CHK_FIFOS, FlexBus_S0_DEQ_FIFOS} FlexBus_States_rd deriving (Bits, Eq, FShow);
217
218 //FlexBus Addr. Data Payload
219
220 typedef struct {
221 Bit #(32) s_AD; // out
222 } FlexBus_Payload
223 deriving (Bits, FShow);
224
225 typedef struct {
226 Bit #(32) din; // in
227 } FlexBus_din
228 deriving (Bits, FShow);
229
230 //FlexBus Attributes
231
232 typedef struct {
233 Bit #(1) s_R_Wn; // out
234 Bit #(2) s_TSIZ; // out
235 } FlexBus_Attr
236 deriving (Bits, FShow);
237
238 typedef struct {
239 Bit #(6) s_FBCSn; // out
240 Bit #(4) s_BEn_BWEn; // out
241 Bit #(1) s_TBSTn; // out
242 Bit #(1) s_OEn; // out
243 } FlexBus_Signals #(numeric type wd_addr, numeric type wd_data)
244 deriving (Bits, FShow);
245
246 // FlexBus Control Signals
247
248 // Bit s_ALE; // out
249 // Bit s_TAn; // in
250
251 /* ----------------------------------------------------------------
252
253 module mkFlexBusTop (Empty);
254 AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(56, 64,10)
255 flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
256
257 endmodule
258
259
260 // ---------------------------------------------------------------- */
261 // AXI4 Lite Slave to FlexBus Master transactor interface
262
263 interface AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(numeric type wd_addr,
264 numeric type wd_data,
265 numeric type wd_user);
266 method Action reset;
267
268 // AXI side
269 interface AXI4_Slave_IFC #(wd_addr, wd_data, wd_user) axi_side;
270
271 // FlexBus side
272 interface FlexBus_Master_IFC flexbus_side;
273
274 endinterface: AXI4_Slave_to_FlexBus_Master_Xactor_IFC
275
276 // ----------------------------------------------------------------
277
278 // AXI4 Lite Slave to FlexBus Master transactor
279
280 module mkAXI4_Slave_to_FlexBus_Master_Xactor
281 (AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(wd_addr, wd_data, wd_user))
282 provisos (Add#(a__, 8, wd_addr),
283 Add#(b__, 64, wd_data),
284 //Bits#(Bit#(56), wd_addr),
285 //Bits#(Bit#(64), wd_data),
286 //Bits#(Bit#(32), wd_fb_addr),
287 //Bits#(Bit#(32), wd_fb_data),
288 //Bits#(Inout#(Bit#(32)), a__),
289 // Bits#(Inout#(Bit#(32)), wd_Fb_addr),
290 //Bits#(Inout#(Bit#(32)), 48),
291 Div#(wd_data, 16, 4));
292 Bool unguarded = True;
293 Bool guarded = False;
294 //let wD_FB_ADDR = valueOf(wd_fb_addr);
295 //let wD_FB_DATA = valueOf(wd_fb_data);
296
297 FlexBus_Register_IFC register_ifc <- mkFlexBus_Registers;
298
299 Reg#(Bit#(32)) r_AD <- mkReg(0);
300 Reg#(Bit#(32)) r_din <- mkReg(0);
301 Reg#(Bit#(1)) r_R_Wn <- mkReg(1'b1);
302 Reg#(Bit#(2)) r_TSIZ <- mkReg(2'b00);
303 Reg#(Bit#(6)) r_FBCSn <- mkReg(6'h3F);
304 Reg#(Bit#(4)) r_BE_BWEn <- mkReg(4'hF);
305 Reg#(Bit#(1)) r_TBSTn <- mkReg(1'b1);
306 Reg#(Bit#(1)) r_OEn <- mkReg(1'b1);
307 Reg#(Bit#(1)) r_ALE <- mkReg(1'b0);
308 Reg#(Bit#(1)) r_ext_TAn <- mkReg(1'b0);
309 Reg#(Bit#(1)) r_int_TAn <- mkReg(1'b1);
310
311 Reg#(Bit#(2)) r_ASET <- mkReg(2'b00);
312 Reg#(Bit#(2)) r_PS <- mkReg(2'b00);
313 Reg#(Bit#(3)) r_rpt_cnt <- mkReg(3'b000);
314 Reg#(Bit#(2)) r_burst_cnt <- mkReg(2'b00);
315 Reg#(Bit#(2)) r_hld_cnt <- mkReg(2'b00);
316 Reg#(Bit#(6)) r_WS_cnt <- mkReg(6'h00);
317 Reg#(Bit#(6)) r_SWS_cnt <- mkReg(6'h00);
318 Reg#(Bit#(wd_addr)) r_awaddr <- mkReg(0);
319 Reg#(Bit#(2)) r_awsize <- mkReg(0);
320 Reg#(Bit#(wd_addr)) r2_awaddr <- mkReg(0);
321 Reg#(Bit#(wd_data)) r_wdata <- mkReg(0);
322 Reg#(AXI4_Resp) r_wrbresp <- mkReg(AXI4_OKAY);
323 Reg#(AXI4_Resp) r_rresp <- mkReg(AXI4_OKAY);
324 Reg#(Bit#(wd_data)) r_rd_data <- mkReg(0);
325 Reg#(Bit#(TDiv#(wd_data,8))) r1_wstrb <- mkReg(0);
326 Reg#(Bit#(TDiv#(wd_data,8))) r2_wstrb <- mkReg(0);
327 Reg#(Bit#(wd_addr)) r_araddr <- mkReg(0);
328 Reg#(Bit#(wd_addr)) r2_araddr <- mkReg(0);
329 Reg#(Bit#(2)) r_arsize <- mkReg(0);
330 Reg#(Bit#(4)) r_arid <- mkReg(0);
331 Reg#(Bit#(4)) r_awid <- mkReg(0);
332 Reg#(Bit#(1)) wr_pending <- mkReg(0);
333 Reg#(Bit#(1)) r_chk_fifos_wr <- mkReg(0);
334 Reg#(Bit#(1)) r_chk_fifos_rd <- mkReg(0);
335 ConfigReg#(Bit#(1)) rd_wrb <- mkConfigReg(1);
336 Reg#(Bool) r_rready <- mkReg(False);
337 Reg#(Bool) r2_rready <- mkReg(False);
338
339 Reg#(Bool) r1_awvalid <- mkReg(False);
340 Reg#(Bool) r2_awvalid <- mkReg(False);
341 Reg#(Bool) r1_wvalid <- mkReg(False);
342 Reg#(Bool) r2_wvalid <- mkReg(False);
343 Reg#(Bool) r1_arvalid <- mkReg(False);
344 Reg#(Bool) r2_arvalid <- mkReg(False);
345
346 Reg#(Bool) r1_OEn <- mkReg(True);
347
348 Reg#(Bit#(8)) r_AD_32bit_data_byte1 <- mkReg(0);
349 Reg#(Bit#(8)) r_AD_32bit_data_byte2 <- mkReg(0);
350 Reg#(Bit#(8)) r_AD_32bit_data_byte3 <- mkReg(0);
351 Reg#(Bit#(8)) r_AD_32bit_data_byte4 <- mkReg(0);
352
353 Reg#(Bit#(8)) r_AD_32bit_addr_byte1 <- mkReg(0);
354 Reg#(Bit#(8)) r_AD_32bit_addr_byte2 <- mkReg(0);
355 Reg#(Bit#(8)) r_AD_32bit_addr_byte3 <- mkReg(0);
356 Reg#(Bit#(8)) r_AD_32bit_addr_byte4 <- mkReg(0);
357
358 Reg#(Bit#(8)) r_rd_data_32bit_byte1 <- mkReg(0);
359 Reg#(Bit#(8)) r_rd_data_32bit_byte2 <- mkReg(0);
360 Reg#(Bit#(8)) r_rd_data_32bit_byte3 <- mkReg(0);
361 Reg#(Bit#(8)) r_rd_data_32bit_byte4 <- mkReg(0);
362
363 Reg#(Bit#(32)) r_MBAR <- mkReg(32'h04000000);
364
365 Reg#(FlexBus_States) flexbus_state <- mkReg(IDLE);
366 Reg#(FlexBus_States_rd) flexbus_state_rd <- mkReg(FlexBus_S0_CHK_FIFOS);
367 Reg#(FlexBus_States_wr) flexbus_state_wr <- mkReg(FlexBus_S0_CHK_FIFOS);
368
369 // These FIFOs are guarded on BSV side, unguarded on AXI side
370 FIFOF #(AXI4_Wr_Addr #(wd_addr, wd_user)) f_wr_addr <- mkGFIFOF (unguarded, guarded);
371 FIFOF #(AXI4_Wr_Data #(wd_data)) f_wr_data <- mkGFIFOF (unguarded, unguarded);
372 FIFOF #(AXI4_Wr_Resp #(wd_user)) f_wr_resp <- mkGFIFOF (guarded, unguarded);
373
374 FIFOF #(AXI4_Rd_Addr #(wd_addr, wd_user)) f_rd_addr <- mkGFIFOF (unguarded, guarded);
375 FIFOF #(AXI4_Rd_Data #(wd_data, wd_user)) f_rd_data <- mkGFIFOF (guarded, unguarded);
376
377 Reg#(Maybe#(Bit#(1))) c_TAn[2] <- mkCReg(2, tagged Invalid);
378 Reg#(Maybe#(Bit#(32))) c_din[2] <- mkCReg(2, tagged Invalid);
379
380 //TriState#(Bit#(32)) tri_AD_out <- mkTriState(r1_OEn,r_AD);
381
382 // ----------------------------------------------------------------
383
384 rule rl_OEn;
385 if (r_OEn == 1'b0)
386 r1_OEn <= False;
387 else
388 r1_OEn <= True;
389 endrule
390
391 rule rl_state_S0_CHK_FIFO_RD(flexbus_state_rd == FlexBus_S0_CHK_FIFOS);
392 `ifdef verbose_debug $display("STATE S0 CHK FIFOS RD FIRED"); `endif
393 if (f_rd_addr.notEmpty) begin
394 register_ifc.inp_side.m_ad_bus(f_rd_addr.first.araddr[31:0]);
395 flexbus_state_rd <= FlexBus_S0_DEQ_FIFOS;
396 `ifdef verbose_debug_l2 $display("READ ADDR FIFO WAS READ FIRST r_araddr=%h \n", f_rd_addr.first.araddr); `endif
397 end
398 endrule
399
400 (* preempts = "rl_check_read_fifo, rl_check_write_fifo" *)
401 rule rl_check_read_fifo (r_chk_fifos_rd == 1'b1 && f_rd_addr.notEmpty);
402 rd_wrb <= 1'b1;
403 r_chk_fifos_rd <= 1'b0;
404 r_chk_fifos_wr <= 1'b0;
405 endrule
406
407 rule rl_check_write_fifo(r_chk_fifos_wr == 1'b1 && f_wr_addr.notEmpty && f_wr_data.notEmpty);
408 if (f_wr_addr.first.awaddr[31:16] != r_MBAR[31:16]) begin
409 rd_wrb <= 1'b0;
410 r_chk_fifos_rd <= 1'b0;
411 r_chk_fifos_wr <= 1'b0;
412 end
413 endrule
414
415 rule rl_state_S0_CHK_FIFOS_WR(flexbus_state_wr == FlexBus_S0_CHK_FIFOS);
416 `ifdef verbose_debug $display("STATE S0 CHK FIFOS WR FIRED"); `endif
417 if (f_wr_addr.notEmpty && f_wr_data.notEmpty) begin
418 if (f_wr_addr.first.awaddr[31:16] == r_MBAR[31:16]) begin
419 f_wr_addr.deq; f_wr_data.deq;
420 end
421 else begin
422 flexbus_state_wr <= FlexBus_S0_DEQ_FIFOS;
423 end
424 register_ifc.inp_side.m_ad_bus(f_wr_addr.first.awaddr[31:0]);
425 register_ifc.inp_side.m_data_bus(f_wr_data.first.wdata[31:0]);
426 end
427 endrule
428
429 rule rl_state_S0_DEQ_FIFOS (flexbus_state_rd == FlexBus_S0_DEQ_FIFOS || flexbus_state_wr == FlexBus_S0_DEQ_FIFOS);
430 `ifdef verbose_debug $display("STATE S0 DEQ FIFOS FIRED"); `endif
431 if (rd_wrb == 1'b1) begin
432 flexbus_state <= FlexBus_S0_DEQ_RD_FIFOS;
433 flexbus_state_rd <= IDLE;
434 flexbus_state_wr <= IDLE;
435 end
436 else if (rd_wrb == 1'b0) begin
437 flexbus_state <= FlexBus_S0_DEQ_WR_FIFOS;
438 flexbus_state_rd <= IDLE;
439 flexbus_state_wr <= IDLE;
440 end
441 if (flexbus_state_rd == FlexBus_S0_DEQ_FIFOS && flexbus_state_wr == FlexBus_S0_DEQ_FIFOS) wr_pending <= 1'b1;
442 endrule
443
444 rule rl_state_S0_DEQ_WR_FIFOS (flexbus_state == FlexBus_S0_DEQ_WR_FIFOS);
445 `ifdef verbose_debug $display("STATE S0 DEQ WR FIFOS FIRED"); `endif
446 r_ASET <= register_ifc.op_side.m_ASET;
447 Bit#(3) v_awsize = 3'b000;
448 if ((f_wr_addr.notEmpty) ) begin
449 r1_awvalid <= f_wr_addr.notEmpty;
450 f_wr_addr.deq;
451 r_chk_fifos_wr <= 1'b1;
452 r_chk_fifos_rd <= 1'b1;
453 AXI4_Wr_Addr#(wd_addr, wd_user) wr_addr = f_wr_addr.first;
454 r_awaddr <= f_wr_addr.first.awaddr;
455 v_awsize = f_wr_addr.first.awsize;
456 r_awid <= f_wr_addr.first.awid;
457 case (v_awsize) matches
458 {3'b000}: r_awsize <= 2'b01;
459 {3'b001}: r_awsize <= 2'b10;
460 {3'b010}: r_awsize <= 2'b00;
461 endcase
462 `ifdef verbose_debug_l2 $display("ADDR FIFO WAS NOT EMPTY SO I DEQUEUED r_awaddr=%h \n", r_awaddr); `endif
463 end
464 if ((f_wr_data.notEmpty) ) begin
465 r1_wvalid <= f_wr_data.notEmpty;
466 f_wr_data.deq;
467 `ifdef verbose_debug_l2 $display("DATA FIFO WAS NOT EMPTY SO I DEQUEUED\n"); `endif
468 AXI4_Wr_Data#(wd_data) wr_data = f_wr_data.first;
469 r_wdata <= f_wr_data.first.wdata;
470 r1_wstrb <= f_wr_data.first.wstrb;
471 `ifdef verbose_debug_l2 $display(" dequeued first r_wdata = %h", r_wdata); `endif
472 end
473 if (f_wr_addr.notEmpty && f_wr_data.notEmpty) begin
474 flexbus_state <= FlexBus_S1_ADDR;
475 end
476 endrule
477
478 rule rl_S0_DEQ_RD_FIFOS (flexbus_state == FlexBus_S0_DEQ_RD_FIFOS);
479 `ifdef verbose_debug $display("STATE S0 DEQ RD FIFOS FIRED"); `endif
480 r_ASET <= register_ifc.op_side.m_ASET;
481 Bit#(3) v_arsize = 3'b000;
482 if ((f_rd_addr.notEmpty) ) begin
483 r1_arvalid <= f_rd_addr.notEmpty;
484 f_rd_addr.deq;
485 r_chk_fifos_wr <= 1'b1;
486 r_chk_fifos_rd <= 1'b1;
487 AXI4_Rd_Addr#(wd_addr, wd_user) rd_addr = f_rd_addr.first;
488 r_araddr <= f_rd_addr.first.araddr;
489 v_arsize = f_rd_addr.first.arsize;
490 r_arid <= f_rd_addr.first.arid;
491 case (v_arsize) matches
492 {3'b000}: r_arsize <= 2'b01;
493 {3'b001}: r_arsize <= 2'b10;
494 {3'b010}: r_arsize <= 2'b00;
495 endcase
496 r_rd_data_32bit_byte1 <= 0;
497 r_rd_data_32bit_byte2 <= 0;
498 r_rd_data_32bit_byte3 <= 0;
499 r_rd_data_32bit_byte4 <= 0;
500 `ifdef verbose_debug_l2 $display("ADDR FIFO WAS NOT EMPTY SO I DEQUEUED r_araddr=%h \n", f_rd_addr.first.araddr); `endif
501 end
502 if (f_rd_addr.notEmpty) begin
503 flexbus_state <= FlexBus_S1_ADDR;
504 end
505 endrule
506
507 rule rl_enq_wr_resp;
508 Bool bready = f_wr_resp.notFull;
509 if (f_wr_resp.notFull)
510 f_wr_resp.enq (AXI4_Wr_Resp {bresp:r_wrbresp,
511 buser:0,
512 bid:r_awid});
513 endrule
514
515
516 rule rl_enq_rd_data;
517 Bool rready = f_rd_data.notFull;
518 if (f_rd_data.notFull && r2_rready) begin
519 f_rd_data.enq (AXI4_Rd_Data {rdata: r_rd_data,
520 rresp: r_rresp,
521 rlast: True,
522 ruser:0,
523 rid:r_arid});
524 //AXI4_Slave_IFC.m_rready(True);
525 `ifdef verbose_debug $display("RD DATA FIFO WAS NOT FULL SO I ENQUEUED r_rd_data=%h r2_rready= %b\n", r_rd_data, r2_rready); `endif
526 end
527 endrule
528
529 rule rl_state_S1_ADDR (flexbus_state == FlexBus_S1_ADDR); //Address state
530 `ifdef verbose_debug $display("STATE S1 FIRED");`endif
531 r_PS <= register_ifc.op_side.m_PS;
532 r_WS_cnt <= register_ifc.op_side.m_WS;
533 r_OEn <= 1'b1;
534 r_BE_BWEn <= 4'hF;
535 r_FBCSn <= 6'h3F;
536 r_ALE <= 1'b1;
537 `ifdef verbose_debug_l2 $display(" r_ASET was ASSIGNED = %b", r_ASET); `endif
538 if (r_rpt_cnt == 3'b000) begin
539 if (r1_arvalid) begin
540 r_AD <= r_araddr[31:0];
541 r_R_Wn <= 1'b1; // Read
542 r_TSIZ <= r_arsize;
543 end
544 else if (r1_awvalid && r1_wvalid) begin
545 r_AD <= r_awaddr[31:0];
546 r_R_Wn <= 1'b0; // WriteBar
547 r_TSIZ <= r_awsize;
548 end
549 end
550 else begin
551 if (r_R_Wn == 1'b0) r_AD <= r_awaddr[31:0];
552 else r_AD <= r_araddr[31:0];
553 r_TBSTn <= 1'b1;
554 r_TSIZ <= register_ifc.op_side.m_PS;
555 end
556 if (( r_ASET != 2'b00) ) begin
557 r_ASET <= r_ASET - 1;
558 end
559 else begin
560 flexbus_state <= FlexBus_S2_WRITE;
561 if (r_rpt_cnt != 3'b000)
562 r_rpt_cnt <= r_rpt_cnt -1;
563 end
564 endrule
565
566 rule rl_assign_AD_bus_reg (flexbus_state == FlexBus_S1_ADDR) ; // Address an Attributes Phase
567 `ifdef verbose_debug_l2 $display(" ASSIGN AD BUS FIRED"); `endif
568
569 r2_awvalid <= r1_awvalid;
570 r2_wvalid <= r1_wvalid;
571 r2_wstrb <= r1_wstrb;
572 r2_arvalid <= r1_arvalid;
573
574 r2_araddr <= r_araddr;
575 r2_awaddr <= r_awaddr;
576
577 r_AD_32bit_data_byte1 <= pack(r_wdata[7:0]);
578 r_AD_32bit_data_byte2 <= pack(r_wdata[15:8]);
579 r_AD_32bit_data_byte3 <= pack(r_wdata[23:16]);
580 r_AD_32bit_data_byte4 <= pack(r_wdata[31:24]);
581 r_AD_32bit_addr_byte1 <= pack(r_awaddr[31:24]);
582 r_AD_32bit_addr_byte2 <= pack(r_awaddr[23:16]);
583 r_AD_32bit_addr_byte3 <= pack(r_awaddr[15:8]);
584 r_AD_32bit_addr_byte4 <= pack(r_awaddr[7:0]);
585 `ifdef verbose_debug_l2 $display("r_wdata after ASSIGN = %h r_PS = %b r_AD_32bit_data_byte1=%h ", r_wdata, r_PS, r_AD_32bit_data_byte1);
586 $display("r_awaddr after ASSIGN = %h r_PS = %b r_AD_32bit_addr_byte1=%h ", r_awaddr, r_PS, r_AD_32bit_addr_byte1); `endif
587 endrule
588
589 rule rl_assign_rd_data;
590 r_rd_data[63:0] <= pack({32'h00000000, r_rd_data_32bit_byte4, r_rd_data_32bit_byte3, r_rd_data_32bit_byte2, r_rd_data_32bit_byte1});
591 r2_rready <= r_rready;
592 `ifdef verbose_debug_l2 $display("ASSIGN READ DATA FIRED AND r_rd_data = %h r_rready=%b r2_rready=%b", r_rd_data, r_rready, r2_rready);`endif
593 endrule
594
595 rule rl_read_ext_signals;
596 if (isValid(c_TAn[1])) begin
597 r_ext_TAn <= fromMaybe(?,c_TAn[1]);
598 c_TAn[1]<= tagged Invalid;
599 end
600 if (isValid(c_din[1])) begin
601 r_din <= fromMaybe(?,c_din[1]);
602 c_din[1]<= tagged Invalid;
603 end
604 //r_din <= tri_AD_out._read;
605 endrule
606
607 rule rl_state_S2_WRITE (flexbus_state == FlexBus_S2_WRITE); //Write Phase
608 `ifdef verbose_debug $display("STATE S2 FIRED"); `endif
609 r_ALE <= 1'b0;
610 r_FBCSn <= register_ifc.op_side.m_FBCSn;
611 r_SWS_cnt <= register_ifc.op_side.m_SWS;
612 if (r_R_Wn == 1'b1)
613 r_hld_cnt <= register_ifc.op_side.m_RDAH;
614 else
615 r_hld_cnt <= register_ifc.op_side.m_WRAH;
616 if (r_R_Wn == 1'b1) begin
617 r_OEn <= 1'b0;
618 if ((register_ifc.op_side.m_BSTR == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
619 r_TBSTn <= 1'b0;
620 end
621 end
622 else begin
623 // ASSIGN WRITE DATA DEPENDING ON BURST INHIBITED OR NOT
624 if ((r_rpt_cnt == 3'b000) ) begin
625 if (r_PS == 2'b01) begin
626 r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
627 end
628 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
629 r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
630 end
631 else begin
632 r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3,r_AD_32bit_data_byte4});
633 end
634 end
635 else if (r_rpt_cnt == 3'b011) begin
636 r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
637 end
638 else if (r_rpt_cnt == 3'b010)
639 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
640 else if (r_rpt_cnt == 3'b001) begin
641 if (r_awsize == 2'b00) begin
642 if ((r_PS == 2'b10) || (r_PS == 2'b11))
643 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
644 else if ((r_PS == 2'b01))
645 r_AD <= pack({r_AD_32bit_data_byte4,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
646 end
647 else if (r_awsize == 2'b10) begin
648 if (r_PS == 2'b01) r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
649
650 end
651 end
652 if (register_ifc.op_side.m_BEM == 1'b1)
653 r_BE_BWEn <= r2_wstrb[3:0];
654 if ((register_ifc.op_side.m_BSTW == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
655 r_TBSTn <= 1'b0;
656 end
657 end
658 if (r_WS_cnt == 6'h00) begin
659 if (r_ext_TAn == 1'b0) begin
660 //r_int_TAn <= 1'b0;
661 flexbus_state <= FlexBus_S3_BURST;
662 end
663 if (register_ifc.op_side.m_AA == 1'b1) begin
664 r_int_TAn <= 1'b1;
665 end
666 r_WS_cnt <= register_ifc.op_side.m_WS;
667 if (r_R_Wn == 1'b1) begin
668 if (r_arsize == 2'b00) begin
669 if ((register_ifc.op_side.m_BSTR == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
670 if (r_PS == 2'b01) r_burst_cnt <= 2'b11;
671 if ((r_PS == 2'b10)||(r_PS == 2'b11)) r_burst_cnt <= 2'b01;
672 end
673 else if ((register_ifc.op_side.m_BSTR == 1'b0) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
674 if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b100;
675 if (((r_PS == 2'b10)||(r_PS == 2'b11)) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
676 end
677 end
678 else if (r_arsize == 2'b10) begin
679 if ((register_ifc.op_side.m_BSTR == 1'b1) && (r_PS == 2'b01)) begin
680 r_burst_cnt <= 2'b01;
681 end
682 else if ((register_ifc.op_side.m_BSTR == 1'b0) && (r_PS == 2'b01)) begin
683 if ((r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
684 end
685 end
686 end
687 else begin
688 if (r_awsize == 2'b00) begin
689 if ((register_ifc.op_side.m_BSTW == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
690 if (r_PS == 2'b01) r_burst_cnt <= 2'b11;
691 if ((r_PS == 2'b10)||(r_PS == 2'b11)) r_burst_cnt <= 2'b01;
692 end
693 else if ((register_ifc.op_side.m_BSTW == 1'b0) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
694 if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b100;
695 if (((r_PS == 2'b10)||(r_PS == 2'b11)) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
696 end
697 end
698 else if (r_awsize == 2'b10) begin
699 if ((register_ifc.op_side.m_BSTW == 1'b1) && (r_PS == 2'b01)) begin
700 r_burst_cnt <= 2'b01;
701 end
702 else if ((register_ifc.op_side.m_BSTW == 1'b0) && (r_PS == 2'b01)) begin
703 if ((r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
704 end
705 end
706 end
707 end
708 else begin
709 r_WS_cnt <= r_WS_cnt -1;
710 end
711 `ifdef verbose_debug_l2 $display("r_AD after WRITE = %h r_ASET=%b r_R_Wn= %b r_PS = %b r_AD_32bit_data_byte1=%h ", r_AD, r_ASET, r_R_Wn, r_PS, r_AD_32bit_data_byte1); `endif
712 endrule
713
714 rule rl_state_S3_BURST (flexbus_state == FlexBus_S3_BURST); // Data Phase with/without bursting terminated prematurely externally
715 `ifdef verbose_debug $display("STATE S3 FIRED"); `endif
716 `ifdef verbose_debug_l2
717 $display("r_rpt_cnt in BURST = %b", r_rpt_cnt);
718 $display("r_burst_cnt in BURST = %b, BSTW=%b", r_burst_cnt,register_ifc.op_side.m_BSTW);
719 $display (" r_AD in BURST = %h", r_AD);
720 $display("r_AD after WRITE = %h r_R_Wn= %b r_PS = %b r_AD_32bit_data_byte1=%h r_AD_32bit_data_byte2=%h r_AD_32bit_data_byte3=%h", r_AD, r_R_Wn, r_PS, r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3);
721 `endif
722 if (r_ext_TAn == 1'b1) begin // premature external termination SLVERR response
723 flexbus_state <= FlexBus_S4_HOLD;
724 if (r_R_Wn == 1'b1) begin
725 r_rresp <= AXI4_SLVERR; //SLVERR
726 end else begin
727 r_wrbresp <= AXI4_SLVERR; //SLVERR
728 end
729 end
730 else if (r_rpt_cnt == 3'b001) begin
731 if (r_R_Wn == 1'b1) begin
732 if (r_arsize == 2'b00) begin
733 if (r_PS == 2'b01) begin
734 r_rd_data_32bit_byte4 <= r_din[7:0];
735 end
736 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
737 r_rd_data_32bit_byte3 <= r_din[7:0];
738 r_rd_data_32bit_byte4 <= r_din[15:8];
739 end
740 end
741 else if (r_arsize == 2'b10) begin
742 if (r_PS == 2'b01)
743 r_rd_data_32bit_byte2 <= r_din[7:0];
744 end
745 r_rready <= True;
746 //r_rpt_cnt <= r_rpt_cnt -1;
747 end
748 //else
749 flexbus_state <= FlexBus_S4_HOLD;
750 if (register_ifc.op_side.m_AA == 1'b1) begin // check this functionality later for now
751 r_OEn <= 1'b1;
752 r_BE_BWEn <= 4'hF;
753 r_FBCSn <= 6'h3F;
754 end
755 end
756 else if (r_rpt_cnt != 3'b000) begin
757 flexbus_state <= FlexBus_S1_ADDR;
758 r_ASET <= register_ifc.op_side.m_ASET;
759 if (register_ifc.op_side.m_AA == 1'b1) begin
760 r_OEn <= 1'b1;
761 r_BE_BWEn <= 4'hF;
762 r_FBCSn <= 6'h3F;
763 end
764 if (r_R_Wn == 1'b1) begin
765 if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b100))
766 r_rd_data_32bit_byte1 <= r_din[7:0];
767 else if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b011))
768 r_rd_data_32bit_byte2 <= r_din[7:0];
769 else if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b010)) begin
770 if (r_arsize == 2'b00)
771 r_rd_data_32bit_byte3 <= r_din[7:0];
772 else if (r_arsize == 2'b10)
773 r_rd_data_32bit_byte1 <= r_din[7:0];
774 end
775 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
776 r_rd_data_32bit_byte1 <= r_din[7:0];
777 r_rd_data_32bit_byte2 <= r_din[15:8];
778 end
779 end
780 end
781 else if (r_burst_cnt == 2'b01) begin
782 if (r_ext_TAn == 1'b1) begin
783 flexbus_state <= FlexBus_S4_HOLD;
784 end
785 else begin
786 if (r_R_Wn == 1'b0) begin
787 if (r_awsize == 2'b00) begin
788 if (r_PS == 2'b01)
789 r_AD <= pack({r_AD_32bit_data_byte4,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
790 else if ((r_PS == 2'b10) || (r_PS == 2'b11))
791 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
792 //else
793 // r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3,r_AD_32bit_data_byte4});
794 end
795 else if (r_awsize == 2'b10) begin
796 if (r_PS == 2'b01) r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
797 end
798 end
799 else begin
800 if (r_arsize == 2'b00) begin
801 if (r_PS == 2'b01)
802 r_rd_data_32bit_byte3 <= r_din[7:0];
803 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
804 r_rd_data_32bit_byte1 <= r_din[7:0];
805 r_rd_data_32bit_byte2 <= r_din[15:8];
806 end
807 end
808 else if (r_arsize == 2'b10) begin
809 if (r_PS == 2'b01)
810 r_rd_data_32bit_byte1 <= r_din[7:0];
811 end
812 end
813 if (register_ifc.op_side.m_SWS_EN == 1'b1) begin
814 if (r_SWS_cnt == 6'h00) begin
815 r_SWS_cnt <= register_ifc.op_side.m_SWS;
816 if (register_ifc.op_side.m_AA == 1'b1) begin
817 r_int_TAn <= 1'b1;
818 r_OEn <= 1'b1;
819 r_BE_BWEn <= 4'hF;
820 r_FBCSn <= 6'h3F;
821 end
822 r_burst_cnt <= r_burst_cnt -1;
823 //flexbus_state <= FlexBus_S4_HOLD;
824 end
825 else begin
826 r_SWS_cnt <= r_SWS_cnt -1;
827 end
828 end
829 else begin
830 if (r_WS_cnt == 6'h00) begin
831 r_WS_cnt <= register_ifc.op_side.m_WS;
832 if (register_ifc.op_side.m_AA == 1'b1) begin
833 r_int_TAn <= 1'b1;
834 r_OEn <= 1'b1;
835 r_BE_BWEn <= 4'hF;
836 r_FBCSn <= 6'h3F;
837 end
838 r_burst_cnt <= r_burst_cnt -1;
839 //flexbus_state <= FlexBus_S4_HOLD;
840 end
841 else
842 r_WS_cnt <= r_WS_cnt - 1;
843 end
844 end
845 end
846 else if (r_burst_cnt != 2'b00) begin
847 if (r_R_Wn == 1'b0) begin
848 if ((r_PS == 2'b01) && (r_burst_cnt == 2'b11))
849 r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
850 else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b10)) begin
851 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
852 end
853 //else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b01))
854 // r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
855 //else if ((r_PS == 2'b10) || (r_PS == 2'b11))
856 // r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
857 end
858 else begin
859 if ((r_PS == 2'b01) && (r_burst_cnt == 2'b11))
860 r_rd_data_32bit_byte1 <= r_din[7:0];
861 else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b10)) begin
862 r_rd_data_32bit_byte2 <= r_din[7:0];
863 end
864 end
865 if (register_ifc.op_side.m_SWS_EN == 1'b1) begin
866 if (r_SWS_cnt == 6'h00) begin
867 r_SWS_cnt <= register_ifc.op_side.m_SWS;
868 if (register_ifc.op_side.m_AA == 1'b1)
869 r_int_TAn <= 1'b1;
870 r_burst_cnt <= r_burst_cnt -1;
871 end
872 else begin
873 r_SWS_cnt <= r_SWS_cnt -1;
874 end
875 end
876 else begin
877 if (r_WS_cnt == 6'h00) begin
878 r_WS_cnt <= register_ifc.op_side.m_WS;
879 if (register_ifc.op_side.m_AA == 1'b1)
880 r_int_TAn <= 1'b1;
881 r_burst_cnt <= r_burst_cnt -1;
882 end
883 else begin
884 r_WS_cnt <= r_WS_cnt - 1;
885 end
886 end
887 end
888 else if (r_burst_cnt == 2'b00) begin
889 flexbus_state <= FlexBus_S4_HOLD;
890 if (r_R_Wn == 1'b1) begin
891 if (r_arsize == 2'b00) begin
892 if (r_PS == 2'b01) begin
893 r_rd_data_32bit_byte4 <= r_din[7:0];
894 end
895 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
896 r_rd_data_32bit_byte3 <= r_din[7:0];
897 r_rd_data_32bit_byte4 <= r_din[15:8];
898 end
899 else begin
900 r_rd_data_32bit_byte1 <= r_din[7:0];
901 r_rd_data_32bit_byte2 <= r_din[15:8];
902 r_rd_data_32bit_byte3 <= r_din[23:16];
903 r_rd_data_32bit_byte4 <= r_din[31:24];
904 end
905 end
906 else if (r_arsize == 2'b10) begin
907 if (r_PS == 2'b01)
908 r_rd_data_32bit_byte2 <= r_din[7:0];
909 //if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
910 else begin
911 r_rd_data_32bit_byte1 <= r_din[7:0];
912 r_rd_data_32bit_byte2 <= r_din[15:8];
913 end
914 end
915 else if (r_arsize == 2'b01) begin
916 r_rd_data_32bit_byte1 <= r_din[7:0];
917 end
918 r_rready <= True;
919 end
920 if (register_ifc.op_side.m_AA == 1'b1) begin // check this functionality later for now
921 r_OEn <= 1'b1;
922 r_BE_BWEn <= 4'hF;
923 r_FBCSn <= 6'h3F;
924 end
925 end
926 endrule
927
928 rule rl_state_S4_HOLD (flexbus_state == FlexBus_S4_HOLD); //Address Phase
929 `ifdef verbose_debug $display("STATE S4 FIRED");`endif
930 r_int_TAn <= 1'b1;
931 r_R_Wn <= 1'b1;
932 r_OEn <= 1'b1;
933 r_BE_BWEn <= 4'hF;
934 r_FBCSn <= 6'h3F;
935 r_TBSTn <= 1'b1;
936 if (r_hld_cnt == 2'b00) begin
937 if (wr_pending == 1'b1) begin
938 flexbus_state <= FlexBus_S0_DEQ_WR_FIFOS;
939 flexbus_state_wr <= IDLE;
940 flexbus_state_rd <= IDLE;
941 wr_pending <= 1'b0;
942 end
943 else begin
944 flexbus_state <= IDLE;
945 flexbus_state_wr <= FlexBus_S0_CHK_FIFOS;
946 flexbus_state_rd <= FlexBus_S0_CHK_FIFOS;
947 end
948 r1_arvalid <= False;
949 r1_awvalid <= False;
950 r1_wvalid <= False;
951
952 r_rready <= False;
953 r_wrbresp <= AXI4_OKAY;
954 r_rresp <= AXI4_OKAY;
955 r_ASET <= 2'b00;
956 r_rpt_cnt <= 3'b000;
957 r_burst_cnt <= 2'b00;
958 r_hld_cnt <= 2'b00;
959 r_WS_cnt <= 6'h00;
960 r_SWS_cnt <= 6'h00;
961 r_awaddr <= 0;
962 r_wdata <= 0;
963 //r_rd_data <= 0;
964 r1_wstrb <= 0;
965 //r2_wstrb <= 0;
966 r_araddr <= 0;
967 end
968 else
969 r_hld_cnt <= r_hld_cnt -1;
970 endrule
971
972 // ----------------------------------------------------------------
973 // INTERFACE
974
975 method Action reset;
976 `ifdef verbose_debug_l2 $display (" I RESET \n"); `endif
977 f_wr_addr.clear;
978 f_wr_data.clear;
979 f_wr_resp.clear;
980 f_rd_addr.clear;
981 f_rd_data.clear;
982
983 c_TAn[0]<= tagged Invalid;
984 c_din[0]<= tagged Invalid;
985 endmethod
986
987 // AXI side
988 interface axi_side = interface AXI4_Slave_IFC;
989
990 // Wr Addr channel
991 method Action m_awvalid (Bool awvalid,
992 Bit #(wd_addr) awaddr,
993 Bit#(3) awsize,
994 Bit #(wd_user) awuser,
995 Bit#(8) awlen,
996 Bit#(2) awburst,
997 Bit#(4) awid
998 );
999 if (awvalid && f_wr_addr.notFull) begin
1000 f_wr_addr.enq (AXI4_Wr_Addr {awaddr: awaddr,
1001 awuser: awuser,
1002 awlen:awlen,
1003 awsize:awsize,
1004 awburst:awburst,
1005 awid:awid});
1006 end
1007 endmethod
1008
1009 method Bool m_awready;
1010 return f_wr_addr.notFull;
1011 endmethod
1012
1013 // Wr Data channel
1014 method Action m_wvalid (Bool wvalid,
1015 Bit #(wd_data) wdata,
1016 Bit #(TDiv #(wd_data, 8)) wstrb,
1017 Bool wlast,
1018 Bit#(4) wid);
1019 if (wvalid && f_wr_data.notFull) begin
1020 f_wr_data.enq (AXI4_Wr_Data {wdata: wdata, wstrb: wstrb, wlast:wlast, wid: wid});
1021 end
1022 endmethod
1023
1024 method Bool m_wready;
1025 return f_wr_data.notFull;
1026 endmethod
1027
1028 // Wr Response channel
1029 method Bool m_bvalid = f_wr_resp.notEmpty;
1030 method Bit #(2) m_bresp = pack (f_wr_resp.first.bresp);
1031 method Bit #(wd_user) m_buser = f_wr_resp.first.buser;
1032 method Bit #(4) m_bid = f_wr_resp.first.bid;
1033 method Action m_bready (Bool bready);
1034 if (bready && f_wr_resp.notEmpty)
1035 f_wr_resp.deq;
1036 endmethod
1037
1038 // Rd Addr channel
1039 method Action m_arvalid (Bool arvalid,
1040 Bit #(wd_addr) araddr,
1041 Bit#(3) arsize,
1042 Bit #(wd_user) aruser,
1043 Bit#(8) arlen,
1044 Bit#(2) arburst,
1045 Bit#(4) arid);
1046 if (arvalid && f_rd_addr.notFull) begin
1047 f_rd_addr.enq (AXI4_Rd_Addr {araddr: araddr,
1048 aruser: aruser,
1049 arlen : arlen,
1050 arsize: arsize,
1051 arburst:arburst,
1052 arid:arid});
1053 end
1054 endmethod
1055
1056 method Bool m_arready;
1057 return f_rd_addr.notFull;
1058 endmethod
1059
1060 // Rd Data channel
1061 method Bool m_rvalid = f_rd_data.notEmpty;
1062 method Bit #(2) m_rresp = pack (f_rd_data.first.rresp);
1063 method Bit #(wd_data) m_rdata = f_rd_data.first.rdata;
1064 method Bool m_rlast = f_rd_data.first.rlast;
1065 method Bit #(wd_user) m_ruser = f_rd_data.first.ruser;
1066 method Bit#(4) m_rid=f_rd_data.first.rid;
1067
1068 method Action m_rready (Bool rready);
1069 if (rready && f_rd_data.notEmpty)
1070 f_rd_data.deq;
1071 endmethod
1072 endinterface;
1073
1074 interface flexbus_side = interface FlexBus_Master_IFC;
1075 //interface io_AD_master = tri_AD_out.io;
1076
1077 interface m_tAn = interface Put
1078 method Action put(Bit#(1) in) if(c_TAn[0] matches tagged Invalid);
1079 c_TAn[0] <= tagged Valid in;
1080 endmethod
1081 endinterface;
1082
1083 interface m_din = interface Put
1084 method Action put(Bit#(32) in) if(c_din[0] matches tagged Invalid);
1085 c_din[0] <= tagged Valid in;
1086 endmethod
1087 endinterface;
1088
1089 interface m_AD = interface Get
1090 method ActionValue#(Bit#(32)) get;
1091 return r_AD;
1092 endmethod
1093 endinterface;
1094
1095 interface m_R_Wn = interface Get
1096 method ActionValue#(Bit#(1)) get;
1097 return r_R_Wn;
1098 endmethod
1099 endinterface;
1100
1101 interface m_TSIZ = interface Get
1102 method ActionValue#(Bit#(2)) get;
1103 return r_TSIZ;
1104 endmethod
1105 endinterface;
1106
1107 interface m_FBCSn = interface Get
1108 method ActionValue#(Bit#(6)) get;
1109 return r_FBCSn;
1110 endmethod
1111 endinterface;
1112
1113 interface m_BWEn = interface Get
1114 method ActionValue#(Bit#(4)) get;
1115 return r_BE_BWEn;
1116 endmethod
1117 endinterface;
1118
1119 interface m_TBSTn = interface Get
1120 method ActionValue#(Bit#(1)) get;
1121 return r_TBSTn;
1122 endmethod
1123 endinterface;
1124
1125 interface m_OE32n = interface Get
1126 method ActionValue#(Bit#(32)) get;
1127 Bit#(32) ten;
1128 for (int i=0; i<32; i=i+1) begin
1129 ten[i] = r_OEn;
1130 end
1131 return ten;
1132 endmethod
1133 endinterface;
1134
1135 interface m_OEn = interface Get
1136 method ActionValue#(Bit#(1)) get;
1137 return r_OEn;
1138 endmethod
1139 endinterface;
1140
1141 interface m_ALE = interface Get
1142 method ActionValue#(Bit#(1)) get;
1143 return r_ALE;
1144 endmethod
1145 endinterface;
1146
1147 //endinterface;
1148
1149 endinterface;
1150
1151 endmodule: mkAXI4_Slave_to_FlexBus_Master_Xactor
1152
1153 module mkFlexBus_Registers (FlexBus_Register_IFC);
1154
1155 // Vectors of Chip Select AR, MR and Control Registers
1156 Vector#(6, Reg#(Bit#(32)) ) vec_addr_regs <- replicateM (mkReg(0));
1157 Vector#(6, Reg#(Bit#(32)) ) vec_mask_regs <- replicateM (mkReg(0));
1158 Vector#(6, Reg#(Bit#(32)) ) vec_cntr_regs <- replicateM (mkReg(0));
1159
1160 // Control Register Fields
1161
1162 Reg#(Bit#(6)) r_FBCSn <- mkReg(6'h3F);
1163 Reg#(Bit#(6)) r_SWS <- mkReg(6'h00);
1164 Reg#(Bit#(1)) r_SWS_EN <- mkReg(1'b0);
1165 Reg#(Bit#(2)) r_ASET <- mkReg(2'b00);
1166 Reg#(Bit#(2)) r_RDAH <- mkReg(2'b00);
1167 Reg#(Bit#(2)) r_WRAH <- mkReg(2'b00);
1168 Reg#(Bit#(6)) r_WS <- mkReg(6'h00);
1169 Reg#(Bit#(1)) r_AA <- mkReg(1'b0);
1170 Reg#(Bit#(2)) r_PS <- mkReg(2'b00);
1171 Reg#(Bit#(1)) r_BEM <- mkReg(1'b0);
1172 Reg#(Bit#(1)) r_BSTR <- mkReg(1'b0);
1173 Reg#(Bit#(1)) r_BSTW <- mkReg(1'b0);
1174
1175 Reg#(Bit#(32)) r_rom_cntr_reg_0 <- mkReg(0);
1176 Reg#(Bit#(32)) r_ad_bus <- mkReg(32'hFFFFFFFF);
1177 Reg#(Bit#(32)) r_data_bus <- mkReg(32'h00000000);
1178 Reg#(Bit#(32)) r_MBAR <- mkReg(32'h04000000);
1179 //------------------------------------------------------------------------
1180
1181 rule rl_write_config_regs;
1182 Bit#(32) v_MBAR = r_MBAR + 'h0500;
1183 for (int i=0; i<6; i=i+1) begin
1184 if ( v_MBAR == r_ad_bus) begin
1185 vec_addr_regs[i][31:16] <= r_data_bus[31:16];
1186 end
1187 v_MBAR = v_MBAR + 'h04;
1188 if ( v_MBAR == r_ad_bus) begin
1189 vec_mask_regs[i] <= r_data_bus;
1190 end
1191 v_MBAR = v_MBAR + 'h04;
1192 if ( v_MBAR == r_ad_bus) begin
1193 vec_cntr_regs[i] <= r_data_bus;
1194 end
1195 v_MBAR = v_MBAR + 'h04;
1196 end
1197 endrule
1198
1199 rule rl_generate_individual_chip_sels;
1200
1201 Bit#(6) chp_sel_vec = 6'h3F;
1202 Bit#(32) r_cntr_reg_sel = 32'h00000000;
1203 for (int i=0; i<6; i=i+1) begin
1204 if ((~vec_mask_regs[i] & vec_addr_regs[i]) == (~vec_mask_regs[i] & pack({r_ad_bus[31:16],16'h0000}))) begin
1205 chp_sel_vec[i] = 1'b0;
1206 end
1207 end
1208 r_FBCSn <= pack({chp_sel_vec[5],chp_sel_vec[4],chp_sel_vec[3],chp_sel_vec[2],chp_sel_vec[1],chp_sel_vec[0]});
1209
1210 case (pack({chp_sel_vec[5],chp_sel_vec[4],chp_sel_vec[3],chp_sel_vec[2],chp_sel_vec[1],chp_sel_vec[0]})) matches
1211 {6'b111110}: r_cntr_reg_sel = vec_cntr_regs[0];
1212 {6'b111101}: r_cntr_reg_sel = vec_cntr_regs[1];
1213 {6'b111011}: r_cntr_reg_sel = vec_cntr_regs[2];
1214 {6'b110111}: r_cntr_reg_sel = vec_cntr_regs[3];
1215 {6'b101111}: r_cntr_reg_sel = vec_cntr_regs[4];
1216 {6'b011111}: r_cntr_reg_sel = vec_cntr_regs[5];
1217 endcase
1218
1219 r_SWS <= r_cntr_reg_sel[31:26];
1220 r_SWS_EN <= r_cntr_reg_sel[23];
1221 r_ASET <= r_cntr_reg_sel[21:20];
1222 r_RDAH <= r_cntr_reg_sel[19:18];
1223 r_WRAH <= r_cntr_reg_sel[17:16];
1224 //r_WS <= r_cntr_reg_sel[15:10];
1225 r_WS <= 6'h06;
1226 r_AA <= r_cntr_reg_sel[8];
1227 r_PS <= r_cntr_reg_sel[7:6];
1228 r_BEM <= r_cntr_reg_sel[5];
1229 r_BSTR <= r_cntr_reg_sel[4];
1230 r_BSTW <= r_cntr_reg_sel[3];
1231 endrule
1232 //-------------------------------------------------------------------------
1233 // FlexBus Register Input Interface
1234 interface inp_side = interface FlexBus_Register_Input_IFC;
1235 method Action reset (Bit #(32) ad_bus);
1236 for (int i=0; i<6; i=i+1)
1237 vec_addr_regs[i] <= 32'h00000000;
1238 for (int i=0; i<6; i=i+1)
1239 vec_mask_regs[i] <= 32'h00000000;
1240 for (int i=0; i<6; i=i+1)
1241 vec_cntr_regs[i] <= 32'h00000000;
1242 r_rom_cntr_reg_0[8] <= ad_bus[2];
1243 r_rom_cntr_reg_0[7:6] <= ad_bus[1:0];
1244 r_rom_cntr_reg_0[5] <= ad_bus[3];
1245 r_rom_cntr_reg_0[15:10] <= 6'h3F;
1246 r_rom_cntr_reg_0[21:16] <= 6'h3F;
1247 vec_cntr_regs[0] <= r_rom_cntr_reg_0;
1248 endmethod
1249 method Action m_ad_bus (Bit #(32) ad_bus);
1250 r_ad_bus <= ad_bus;
1251 endmethod
1252 method Action m_data_bus (Bit #(32) data_bus);
1253 r_data_bus <= data_bus;
1254 endmethod
1255 endinterface;
1256
1257 // FlexBus Register Output Interface
1258 interface op_side = interface FlexBus_Register_Output_IFC;
1259 method Bit#(6) m_FBCSn ();
1260 return r_FBCSn;
1261 endmethod
1262 method Bit#(6) m_SWS ();
1263 return r_SWS;
1264 endmethod
1265 method Bit#(1) m_SWS_EN ();
1266 return r_SWS_EN;
1267 endmethod
1268 method Bit#(2) m_ASET ();
1269 return r_ASET;
1270 endmethod
1271 method Bit#(2) m_RDAH ();
1272 return r_RDAH;
1273 endmethod
1274 method Bit#(2) m_WRAH ();
1275 return r_WRAH;
1276 endmethod
1277 method Bit#(6) m_WS ();
1278 return r_WS;
1279 endmethod
1280 method Bit#(1) m_AA ();
1281 return r_AA;
1282 endmethod
1283 method Bit#(2) m_PS ();
1284 return r_PS;
1285 endmethod
1286 method Bit#(1) m_BEM ();
1287 return r_BEM;
1288 endmethod
1289 method Bit#(1) m_BSTR ();
1290 return r_BSTR;
1291 endmethod
1292 method Bit#(1) m_BSTW ();
1293 return r_BSTW;
1294 endmethod
1295 endinterface;
1296
1297 endmodule: mkFlexBus_Registers
1298
1299 `ifdef TESTING
1300 module mkVerfn_Top (Empty);
1301
1302 /*
1303 FlexBus_Slave_to_AXI4_Master_Fabric_IFC#(32,32,4)
1304 verfn_ifc <- mkFlexBus_Slave_to_AXI4_Master_Fabric;
1305 AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(32, 32, 4)
1306 flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
1307
1308 mkConnection(flexbus_xactor_ifc.flexbus_side,verfn_ifc.flexbus_side);
1309 */
1310
1311 AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(56, 64,10)
1312 flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
1313
1314 endmodule
1315 `endif
1316
1317 endpackage
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