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[shakti-peripherals.git] / src / peripherals / jtagdtm / jtagdtm.bsv
1 /*
2 Copyright (c) 2013, IIT Madras
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
6
7 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
8 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
9 * Neither the name of IIT Madras nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
10
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
13 */
14 package jtagdtm;
15 /*====== Package imports ======= */
16 import Clocks::*;
17 import ConcatReg::*;
18 import FIFO::*;
19 import FIFOF::*;
20 import SpecialFIFOs::*;
21 import DReg::*;
22 /*======= Project imports ===== */
23 `include "jtagdefines.bsv"
24 import defined_types::*;
25 /*============================== */
26
27 interface Ifc_jtagdtm;
28 /*======== Scan input pins ===== */
29 (*always_enabled,always_ready*)
30 method Action scan_out_1_i(Bit#(1) scan_out_1);
31 (*always_enabled,always_ready*)
32 method Action scan_out_2_i(Bit#(1) scan_out_2);
33 (*always_enabled,always_ready*)
34 method Action scan_out_3_i(Bit#(1) scan_out_3);
35 (*always_enabled,always_ready*)
36 method Action scan_out_4_i(Bit#(1) scan_out_4);
37 (*always_enabled,always_ready*)
38 method Action scan_out_5_i(Bit#(1) scan_out_5);
39 /*======= SCAN Output Pins ====== */
40 (*always_enabled,always_ready*)
41 method Bit#(1) scan_in_1;
42 (*always_enabled,always_ready*)
43 method Bit#(1) scan_in_2;
44 (*always_enabled,always_ready*)
45 method Bit#(1) scan_in_3;
46 (*always_enabled,always_ready*)
47 method Bit#(1) scan_in_4;
48 (*always_enabled,always_ready*)
49 method Bit#(1) scan_in_5;
50 (*always_enabled,always_ready*)
51 method Bit#(1) scan_en;
52 (*always_enabled,always_ready*)
53 method Bit#(1) scan_mode_te;
54 /*======= BOUNDARY SCAN Output Pin ====== */
55 (*always_enabled,always_ready*)
56 method Action bs_chain_i(Bit#(1) bs_chain);
57 /*======= BOUNDARY SCAN input Pins ====== */
58 (*always_enabled,always_ready*)
59 method Bit#(1) shiftBscan2Edge;
60 (*always_enabled,always_ready*)
61 method Bit#(1) selectJtagInput;
62 (*always_enabled,always_ready*)
63 method Bit#(1) selectJtagOutput;
64 (*always_enabled,always_ready*)
65 method Bit#(1) updateBscan;
66 (*always_enabled,always_ready*)
67 method Bit#(1) bscan_in;
68 (*always_enabled,always_ready*)
69 method Bit#(1) scan_shift_en;
70 /*======== JTAG input pins ===== */
71 (*always_enabled,always_ready*)
72 method Action tms_i(Bit#(1) tms);
73 (*always_enabled,always_ready*)
74 method Action tdi_i(Bit#(1) tdi);
75 /*==== inputs from Sub-modules === */
76 method Action debug_tdi_i(Bit#(1) debug_tdi);
77 /*======= JTAG Output Pins ====== */
78 (*always_enabled,always_ready*)
79 method Bit#(1) tdo;
80 method Bit#(1) tdo_oe;
81 /*======== TAP States ============= */
82 method Bit#(1) shift_dr;
83 method Bit#(1) pause_dr;
84 method Bit#(1) update_dr;
85 method Bit#(1) capture_dr;
86 /*=========== Output for BS Chain ==== */
87 method Bit#(1) extest_select;
88 method Bit#(1) sample_preload_select;
89 method Bit#(1) debug_select;
90 method Bit#(1) debug_tdo;
91 /*================================ */
92 method Action response_from_dm(Bit#(34) responsedm);
93 method ActionValue#(Bit#(40)) request_to_dm;
94
95 endinterface
96
97 function Reg#(t) readOnlyReg(t r);
98 return (interface Reg;
99 method t _read = r;
100 method Action _write(t x) = noAction;
101 endinterface);
102 endfunction
103 function Reg#(Bit#(1)) condwriteSideEffect(Reg#(Bit#(1)) r, Action a);
104 return (interface Reg;
105 method Bit#(1) _read = r._read;
106 method Action _write(Bit#(1) x);
107 r._write(x);
108 if(x==1)
109 a;
110 endmethod
111 endinterface);
112 endfunction
113
114
115
116 typedef enum {TestLogicReset = 4'h0, RunTestIdle = 4'h1, SelectDRScan = 4'h2,
117 CaptureDR = 4'h3, ShiftDR = 4'h4, Exit1DR = 4'h5,
118 PauseDR = 4'h6, Exit2DR = 4'h7, UpdateDR = 4'h8,
119 SelectIRScan = 4'h9, CaptureIR = 4'ha, ShiftIR = 4'hb,
120 Exit1IR = 4'hc, PauseIR = 4'hd, Exit2IR = 4'he,
121 UpdateIR = 4'hf } TapStates deriving(Bits,Eq,FShow);
122
123 (*synthesize*)
124 (*descending_urgency="scan_logic,scan_shift_en"*)
125 module mkjtagdtm(Ifc_jtagdtm);
126 Clock def_clk<-exposeCurrentClock;
127 Clock invert_clock<-invertCurrentClock;
128 Reset invert_reset<-mkAsyncResetFromCR(0,invert_clock);
129
130 /*========= FIFOs to communicate with the DM==== */
131 FIFOF#(Bit#(40)) request_to_DM <-mkUGFIFOF1();
132 FIFOF#(Bit#(34)) response_from_DM <-mkUGFIFOF1();
133 /*================================================ */
134
135 /*=== Wires to capture the input pins === */
136 Wire#(Bit#(1)) wr_tms<-mkDWire(0);
137 Wire#(Bit#(1)) wr_tdi<-mkDWire(0);
138 Reg#(Bit#(1)) wr_debug_tdi<-mkRegA(0);
139 Reg#(Bit#(1)) wr_bs_chain_tdo<-mkRegA(0);
140 /*======================================== */
141
142 Wire#(Bit#(1)) wr_scan_in_1_all <-mkDWire(0);
143 Wire#(Bit#(1)) wr_scan_in_2_out1 <-mkDWire(0);
144 Wire#(Bit#(1)) wr_scan_in_3_out2 <-mkDWire(0);
145 Wire#(Bit#(1)) wr_scan_in_4_out3 <-mkDWire(0);
146 Wire#(Bit#(1)) wr_scan_in_5_out4 <-mkDWire(0);
147 Reg#(Bit#(1)) wr_scan_shift_en[2] <-mkCRegA(2,0);
148
149 Reg#(TapStates) tapstate<-mkRegA(TestLogicReset);
150 Reg#(Bit#(5)) instruction_shiftreg<-mkRegA(0);
151 Reg#(Bit#(5)) instruction<-mkRegA(`IDCODE, clocked_by invert_clock, reset_by invert_reset); // clock this by the inverted clock
152 Reg#(Bit#(1)) bypass_sr<-mkRegA(0);
153 Reg#(Bit#(1)) scan1_sr <-mkRegA(0);
154 Reg#(Bit#(1)) scan2_sr <-mkRegA(0);
155 Reg#(Bit#(1)) scan3_sr <-mkRegA(0);
156 Reg#(Bit#(1)) scan4_sr <-mkRegA(0);
157 Reg#(Bit#(1)) scan5_sr <-mkRegA(0);
158 Reg#(Bit#(1)) scanall_sr<-mkRegA(0);
159 Reg#(Bit#(1)) scan_en_sr<-mkRegA(0);
160 Reg#(Bit#(1)) scan_mode_te_sr<-mkRegA(0);
161 Reg#(Bit#(1)) full_scan_en_sr<-mkRegA(0);
162 Reg#(Bit#(1)) scan_out_1_sr<-mkRegA(0);
163 Reg#(Bit#(1)) scan_out_2_sr<-mkRegA(0);
164 Reg#(Bit#(1)) scan_out_3_sr<-mkRegA(0);
165 Reg#(Bit#(1)) scan_out_4_sr<-mkRegA(0);
166 Reg#(Bit#(1)) scan_out_5_sr<-mkRegA(0);
167 Wire#(Bit#(1)) shiftBscan2Edge_sr<-mkDWire(0);
168 Wire#(Bit#(1)) selectJtagInput_sr<-mkDWire(0);
169 Wire#(Bit#(1)) selectJtagOutput_sr<-mkDWire(0);
170 Wire#(Bit#(1)) updateBscan_sr<-mkDWire(0);
171 Reg#(Bit#(1)) bs_sr<-mkRegA(0);
172 Reg#(Bit#(32)) idcode_sr<-mkRegA(`IDCODEVALUE);
173
174 Wire#(Bool) wr_dmihardreset_generated<-mkDWire(False);
175 Reg#(Bit#(1)) rg_dmihardreset<-mkRegA(0);
176 Reg#(Bit#(1)) dmihardreset=condwriteSideEffect(rg_dmihardreset,wr_dmihardreset_generated._write(True));
177 Wire#(Bool) wr_dmireset_generated<-mkDWire(False);
178 Reg#(Bit#(1)) rg_dmireset<-mkDReg(0);
179 Reg#(Bit#(1)) dmireset=condwriteSideEffect(rg_dmireset,wr_dmireset_generated._write(True));
180 Reg#(Bit#(3)) idle=readOnlyReg(3'd7);
181 Reg#(Bit#(2)) dmistat<-mkRegA(0);
182 Reg#(Bit#(6)) abits =readOnlyReg(6'd6);
183 Reg#(Bit#(4)) version = readOnlyReg('d1);
184 Reg#(Bit#(32)) dtmcontrol=concatReg8(readOnlyReg(14'd0),
185 dmihardreset,dmireset,readOnlyReg(1'd0),
186 idle,readOnlyReg(dmistat),abits,version);
187 Reg#(Bit#(32)) dtmcontrol_shiftreg<-mkRegA({17'd0,3'd7,2'd0,6'd6,4'd1});
188
189 Reg#(Bit#(40)) dmiaccess_shiftreg[2]<-mkCReg(2,'d2);
190 Reg#(Bit#(2)) response_status<-mkReg(0);
191 Reg#(Bool) capture_repsonse_from_dm<-mkRegA(False);
192 Reg#(Bit#(1)) rg_tdo<-mkRegA(0, clocked_by invert_clock, reset_by invert_reset);
193
194 ReadOnly#(TapStates) crossed_tapstate <-mkNullCrossingWire(invert_clock,tapstate);
195 ReadOnly#(Bit#(5)) crossed_instruction_shiftreg<-mkNullCrossingWire(invert_clock,instruction_shiftreg);
196 ReadOnly#(Bit#(5)) crossed_instruction <-mkNullCrossingWire(def_clk,instruction);
197 ReadOnly#(Bit#(1)) crossed_scan_out_1_sr <-mkNullCrossingWire(invert_clock,scan_out_1_sr);
198 ReadOnly#(Bit#(1)) crossed_scan_out_2_sr <-mkNullCrossingWire(invert_clock,scan_out_2_sr);
199 ReadOnly#(Bit#(1)) crossed_scan_out_3_sr <-mkNullCrossingWire(invert_clock,scan_out_3_sr);
200 ReadOnly#(Bit#(1)) crossed_scan_out_4_sr <-mkNullCrossingWire(invert_clock,scan_out_4_sr);
201 ReadOnly#(Bit#(1)) crossed_scan_out_5_sr <-mkNullCrossingWire(invert_clock,scan_out_5_sr);
202 ReadOnly#(Bit#(1)) crossed_scan_en_sr <-mkNullCrossingWire(invert_clock,scan_en_sr);
203 ReadOnly#(Bit#(1)) crossed_scan_mode_te_sr <-mkNullCrossingWire(invert_clock,scan_mode_te_sr);
204 ReadOnly#(Bit#(1)) crossed_full_scan_en_sr <-mkNullCrossingWire(invert_clock,full_scan_en_sr);
205 ReadOnly#(Bit#(1)) crossed_bypass_sr <-mkNullCrossingWire(invert_clock,bypass_sr);
206 ReadOnly#(Bit#(32)) crossed_idcode_sr <-mkNullCrossingWire(invert_clock,idcode_sr);
207 ReadOnly#(Bit#(1)) crossed_bs_chain_tdo <-mkNullCrossingWire(invert_clock,wr_bs_chain_tdo);
208 ReadOnly#(Bit#(1)) crossed_debug_tdi <-mkNullCrossingWire(invert_clock,wr_debug_tdi);
209 ReadOnly#(Bit#(32)) crossed_dtmcontrol_shiftreg<-mkNullCrossingWire(invert_clock,dtmcontrol_shiftreg);
210 ReadOnly#(Bit#(1)) crossed_output_tdo<-mkNullCrossingWire(def_clk,rg_tdo);
211 ReadOnly#(Bit#(40)) crossed_dmiaccess_shiftreg<-mkNullCrossingWire(invert_clock,dmiaccess_shiftreg[0]);
212
213 Bit#(1) bypass_sel = crossed_instruction == `BYPASS?1:0;
214 Bit#(1) scan_en_sel = crossed_instruction == `SCANEN?1:0;
215 Bit#(1) scan_mode_te_sel = crossed_instruction == `SCANMODE_TE?1:0;
216 Bit#(1) scan1_sel = crossed_instruction == `SCAN1?1:0;
217 Bit#(1) scan2_sel = crossed_instruction == `SCAN2?1:0;
218 Bit#(1) scan3_sel = crossed_instruction == `SCAN3?1:0;
219 Bit#(1) scan4_sel = crossed_instruction == `SCAN4?1:0;
220 Bit#(1) scan5_sel = crossed_instruction == `SCAN5?1:0;
221 Bit#(1) scanall_sel = crossed_instruction == `SCANALL?1:0;
222 Bit#(1) full_scan_en_sel = crossed_instruction == `FULLSCANEN?1:0;
223 Bit#(1) idcode_sel = crossed_instruction == `IDCODE?1:0;
224 Bit#(1) dbg_sel = crossed_instruction == `DEBUG?1:0;
225 Bit#(1) dtmcontrol_sel = crossed_instruction == `DTMCONTROL?1:0;
226 Bit#(1) dmi_sel = crossed_instruction == `DMIACCESS?1:0;
227 Bit#(1) extest_select=crossed_instruction==`EXTEST?1:0;
228 Bit#(1) sample_preload_select=crossed_instruction==`SAMPLE_PRELOAD?1:0;
229
230 Bit#(1) instruction_tdo=crossed_instruction_shiftreg[0];
231 Bit#(1) bypass_tdo=crossed_bypass_sr;
232 Bit#(1) scan_en_tdo=crossed_scan_en_sr;
233 Bit#(1) scan_mode_te_tdo=crossed_scan_mode_te_sr;
234 Bit#(1) full_scan_en_tdo=crossed_full_scan_en_sr;
235 Bit#(1) scan_out_1_tdo=crossed_scan_out_1_sr;
236 Bit#(1) scan_out_2_tdo=crossed_scan_out_2_sr;
237 Bit#(1) scan_out_3_tdo=crossed_scan_out_3_sr;
238 Bit#(1) scan_out_4_tdo=crossed_scan_out_4_sr;
239 Bit#(1) scan_out_5_tdo=crossed_scan_out_5_sr;
240 Bit#(1) idcode_tdo=crossed_idcode_sr[0];
241 Bit#(1) dtmcontrol_tdo=crossed_dtmcontrol_shiftreg[0];
242 Bit#(1) dmiaccess_tdo=crossed_dmiaccess_shiftreg[0][0];
243
244
245
246 /*== This rule implements the TAPs STATE MACHINE====== */
247 rule just_display;
248 `ifdef verbose $display($time,"\tTAPSTATE: ",fshow(tapstate),"\tINSTRUCTION: %h",instruction_shiftreg); `endif
249 endrule
250 rule tap_state_machine;
251 case(tapstate)
252 TestLogicReset: if(wr_tms==0) tapstate<=RunTestIdle;
253 RunTestIdle : if(wr_tms==1) tapstate <= SelectDRScan;
254 SelectDRScan : if(wr_tms==1) tapstate <= SelectIRScan;
255 else tapstate <= CaptureDR;
256 CaptureDR : if(wr_tms==0) tapstate <= ShiftDR;
257 else tapstate <= Exit1DR;
258 ShiftDR : if(wr_tms==1) tapstate <= Exit1DR;
259 Exit1DR : if(wr_tms==0) tapstate <= PauseDR;
260 else tapstate <= UpdateDR;
261 PauseDR : if(wr_tms==1) tapstate <= Exit2DR;
262 Exit2DR : if(wr_tms==1) tapstate <= UpdateDR;
263 else tapstate <= ShiftDR;
264 UpdateDR : if(wr_tms==1) tapstate <= SelectDRScan;
265 else tapstate <= RunTestIdle;
266 SelectIRScan : if(wr_tms==1) tapstate <= TestLogicReset;
267 else tapstate <= CaptureIR;
268 CaptureIR : if(wr_tms==0) tapstate <= ShiftIR;
269 else tapstate <= Exit1IR;
270 ShiftIR : if(wr_tms==1) tapstate <= Exit1IR;
271 Exit1IR : if(wr_tms==0) tapstate <= PauseIR;
272 else tapstate <= UpdateIR;
273 PauseIR : if(wr_tms==1) tapstate <= Exit2IR;
274 Exit2IR : if(wr_tms==1) tapstate <= UpdateIR;
275 else tapstate <= ShiftIR;
276 UpdateIR : if(wr_tms==1) tapstate <= SelectDRScan;
277 else tapstate <= RunTestIdle;
278 default : tapstate <= TestLogicReset;
279 endcase
280 endrule
281
282 rule dmireset_generated(wr_dmireset_generated);
283 `ifdef verbose $display($time,"\tDTM: Received DMIRESET"); `endif
284 dmiaccess_shiftreg[1][1:0]<='d0;
285 response_status<=0;
286 capture_repsonse_from_dm<=False;
287 endrule
288 rule dmihardreset_generated(wr_dmihardreset_generated);
289 request_to_DM.deq;
290 response_from_DM.deq;
291 capture_repsonse_from_dm<=False;
292 endrule
293
294 /*======= perform dtmcontrol shifts ======== */
295 rule shift_dtm;
296 case(tapstate)
297 TestLogicReset: dtmcontrol<={17'd0,idle,2'b0,abits,version};
298 CaptureDR: if(dtmcontrol_sel==1) dtmcontrol_shiftreg<=dtmcontrol;
299 ShiftDR: if(dtmcontrol_sel==1) dtmcontrol_shiftreg<={wr_tdi,dtmcontrol_shiftreg[31:1]};
300 UpdateDR: if(dtmcontrol_sel==1) dtmcontrol<=dtmcontrol_shiftreg;
301 endcase
302 endrule
303 /*========================================== */
304 /*======= perform dmiaccess shifts ======== */
305 rule shift_dmiaccess(!wr_dmihardreset_generated);
306 case(tapstate)
307 TestLogicReset: dmiaccess_shiftreg[0]<='d0;
308 CaptureDR: if(dmi_sel==1)
309 if(response_from_DM.notEmpty)begin
310 let x=response_from_DM.first[33:0];
311 `ifdef verbose $display($time,"\tDTM: Getting response: data %h op: %h",x[33:2],x[1:0]); `endif
312 x[1:0]=x[1:0]|response_status;// keeping the lower 2 bits sticky
313 dmiaccess_shiftreg[0][33:0]<=x;
314 response_status<=x[1:0];
315 response_from_DM.deq;
316 `ifdef verbose $display($time,"\tDTM: New DMIACCESS value: %h",x); `endif
317 capture_repsonse_from_dm<=False;
318 dmistat<=x[1:0];
319 end
320 else begin
321 if(capture_repsonse_from_dm)
322 response_status<=3;
323 `ifdef verbose $display($time,"\tDTM: RESPONSE NOT AVAILABLE. DMIACCESS: %h",dmiaccess_shiftreg[0]); `endif
324 end
325 ShiftDR: if(dmi_sel==1) dmiaccess_shiftreg[0]<={wr_tdi,dmiaccess_shiftreg[0][39:1]};
326 UpdateDR: if(dmi_sel==1)
327 if(request_to_DM.notFull && dmiaccess_shiftreg[0][1:0]!=0 && capture_repsonse_from_dm==False)begin
328 request_to_DM.enq(dmiaccess_shiftreg[0]);
329 dmiaccess_shiftreg[0][1:0]<='d3;
330 capture_repsonse_from_dm<=True;
331 `ifdef verbose $display($time,"\tDTM: Sending request to Debug: %h",dmiaccess_shiftreg[0]); `endif
332 end
333 else begin
334 `ifdef verbose $display($time,"\tDTM: REQUEST NOT SERVED capture: %b DMIACCESS: %h",capture_repsonse_from_dm,dmiaccess_shiftreg[0]); `endif
335 // dmistat<=3;
336 // response_from_DM.enq('d3);
337 end
338 endcase
339 endrule
340 /*========================================== */
341
342 /*== perform instruction register shifts === */
343 rule shift_reg;
344 case(tapstate)
345 CaptureIR: instruction_shiftreg<='b10101;
346 ShiftIR : instruction_shiftreg<= {wr_tdi,instruction_shiftreg[4:1]};
347 endcase
348 endrule
349 rule transfer_instruction_on_nedge; // TODO negedge here
350 case(crossed_tapstate)
351 TestLogicReset :instruction<=`IDCODE;
352 UpdateIR :instruction<=crossed_instruction_shiftreg;
353 endcase
354 endrule
355
356 /*==== Bypass Section === */
357 rule bypass_logic;
358 case(tapstate)
359 TestLogicReset: bypass_sr<=1'b0;
360 CaptureDR : if(bypass_sel==1) bypass_sr<=1'b0;
361 ShiftDR : if(bypass_sel==1) bypass_sr<=wr_tdi;
362 endcase
363 endrule
364
365 /*==== Boundary Scan Section === */
366 rule bs_logic;
367 case(tapstate)
368 TestLogicReset: bs_sr<=1'b0;
369 CaptureDR : begin
370 if(extest_select==1) begin
371 shiftBscan2Edge_sr <= 1'b0;
372 selectJtagInput_sr <= 1'b0;
373 selectJtagOutput_sr <= 1'b0;
374 updateBscan_sr <= 1'b0;
375 bs_sr<=1'b0;
376 end else if (sample_preload_select ==1) begin
377 shiftBscan2Edge_sr <= 1'b0;
378 selectJtagInput_sr <= 1'b0;
379 selectJtagOutput_sr <= 1'b0;
380 bs_sr<=1'b0;
381 end
382 end
383 ShiftDR : begin
384 if(extest_select==1) begin
385 shiftBscan2Edge_sr <= 1'b1;
386 selectJtagInput_sr <= 1'b0;
387 selectJtagOutput_sr <= 1'b0;
388 updateBscan_sr <= 1'b0;
389 bs_sr<=wr_tdi;
390 end else if (sample_preload_select ==1) begin
391 bs_sr<=wr_tdi;
392 shiftBscan2Edge_sr <= 1'b1;
393 end
394 end
395 UpdateDR : begin
396 if(extest_select==1) begin
397 shiftBscan2Edge_sr <= 1'b1;
398 selectJtagInput_sr <= 1'b1;
399 selectJtagOutput_sr <= 1'b1;
400 updateBscan_sr <= 1'b1;
401 end
402 end
403 endcase
404 endrule
405
406 /*==== Scan Chain Section === */
407 rule scan_logic;
408 case(tapstate)
409 TestLogicReset: begin
410 scan_en_sr<=1'b0;
411 scan_mode_te_sr<=1'b0;
412 scan1_sr<=1'b0;
413 scan2_sr<=1'b0;
414 scan3_sr<=1'b0;
415 scan4_sr<=1'b0;
416 scan5_sr<=1'b0;
417 scanall_sr<=1'b0;
418 full_scan_en_sr<=1'b0;
419 wr_scan_shift_en[0]<=1'b0;
420 end
421 CaptureDR : begin
422 if(scan_en_sel==1) scan_en_sr<=1'b0;
423 else if(scan_mode_te_sel==1) scan_mode_te_sr<=1'b0;
424 else if(scan1_sel==1) scan1_sr<=1'b0;
425 else if(scan2_sel==1) scan2_sr<=1'b0;
426 else if(scan3_sel==1) scan3_sr<=1'b0;
427 else if(scan4_sel==1) scan4_sr<=1'b0;
428 else if(scan5_sel==1) scan5_sr<=1'b0;
429 else if(scanall_sel==1) scanall_sr<=1'b0;
430 else if(full_scan_en_sel==1) full_scan_en_sr<=1'b0;
431 wr_scan_shift_en[0]<=1'b0;
432 end
433 ShiftDR : begin
434 if(scan_en_sel==1) scan_en_sr<=wr_tdi;
435 else if(scan_mode_te_sel==1) scan_mode_te_sr<=wr_tdi;
436 else if(scan1_sel==1) scan1_sr<=wr_tdi;
437 else if(scan2_sel==1) scan2_sr<=wr_tdi;
438 else if(scan3_sel==1) scan3_sr<=wr_tdi;
439 else if(scan4_sel==1) scan4_sr<=wr_tdi;
440 else if(scan5_sel==1) scan5_sr<=wr_tdi;
441 else if(scanall_sel==1) scanall_sr<=wr_tdi;
442 else if(full_scan_en_sel==1) full_scan_en_sr<=wr_tdi;
443 if ((scan1_sel == 1'b1 || scan2_sel == 1'b1|| scan3_sel == 1'b1|| scan4_sel == 1'b1|| scan5_sel == 1'b1|| scanall_sel == 1'b1) || (scan_en_sel == 1'b1 && wr_tdi == 1'b0)) wr_scan_shift_en[1] <=1'b1;
444 end
445 UpdateDR : wr_scan_shift_en[0] <=1'b0;
446 endcase
447 endrule
448
449 rule full_scan_mux_logic;
450 if (full_scan_en_sr == 1'b1) begin
451 wr_scan_in_1_all <= scanall_sr;
452 wr_scan_in_2_out1 <= scan_out_1_sr;
453 wr_scan_in_3_out2 <= scan_out_2_sr;
454 wr_scan_in_4_out3 <= scan_out_3_sr;
455 wr_scan_in_5_out4 <= scan_out_4_sr;
456 end
457 else begin
458 wr_scan_in_1_all <= scan1_sr;
459 wr_scan_in_2_out1 <= scan2_sr;
460 wr_scan_in_3_out2 <= scan3_sr;
461 wr_scan_in_4_out3 <= scan4_sr;
462 wr_scan_in_5_out4 <= scan5_sr;
463 end
464 endrule
465
466 /*======= IDCODE section === */
467 rule idcode_logic;
468 case(tapstate)
469 TestLogicReset:idcode_sr<=`IDCODEVALUE;
470 CaptureDR: if(idcode_sel==1) idcode_sr<=`IDCODEVALUE;
471 ShiftDR : if(idcode_sel==1) idcode_sr<={wr_tdi,idcode_sr[31:1]};
472 endcase
473 endrule
474
475 rule generate_tdo_outputpin;
476 if(crossed_tapstate==ShiftIR)
477 rg_tdo<=instruction_tdo;
478 else
479 case(instruction)
480 `IDCODE: rg_tdo<=idcode_tdo;
481 `DEBUG : rg_tdo<=crossed_debug_tdi;
482 `EXTEST: rg_tdo<=crossed_bs_chain_tdo;
483 `SAMPLE_PRELOAD: rg_tdo<=crossed_bs_chain_tdo;
484 `BYPASS: rg_tdo<=bypass_tdo;
485 `SCANEN: rg_tdo<=scan_en_tdo;
486 `SCANMODE_TE: rg_tdo<=scan_mode_te_tdo;
487 `FULLSCANEN: rg_tdo<=full_scan_en_tdo;
488 `SCAN1: rg_tdo <= scan_out_1_tdo;
489 `SCAN2: rg_tdo <= scan_out_2_tdo;
490 `SCAN3: rg_tdo <= scan_out_3_tdo;
491 `SCAN4: rg_tdo <= scan_out_4_tdo;
492 `SCAN5: rg_tdo <= scan_out_5_tdo;
493 `SCANALL: rg_tdo <= scan_out_5_tdo;
494 `DTMCONTROL: rg_tdo<=dtmcontrol_tdo;
495 `DMIACCESS: rg_tdo<=dmiaccess_tdo;
496 default: rg_tdo<=bypass_tdo;
497 endcase
498 endrule
499
500 /*======== SCAN input (scan chain outputs) pins ===== */
501 method Action scan_out_1_i(Bit#(1) scan_out_1);
502 scan_out_1_sr<=scan_out_1;
503 endmethod
504 method Action scan_out_2_i(Bit#(1) scan_out_2);
505 scan_out_2_sr<=scan_out_2;
506 endmethod
507 method Action scan_out_3_i(Bit#(1) scan_out_3);
508 scan_out_3_sr<=scan_out_3;
509 endmethod
510 method Action scan_out_4_i(Bit#(1) scan_out_4);
511 scan_out_4_sr<=scan_out_4;
512 endmethod
513 method Action scan_out_5_i(Bit#(1) scan_out_5);
514 scan_out_5_sr<=scan_out_5;
515 endmethod
516 /*======== JTAG input pins ===== */
517 method Action tms_i(Bit#(1) tms);
518 wr_tms<=tms;
519 endmethod
520 method Action tdi_i(Bit#(1) tdi);
521 wr_tdi<=tdi;
522 endmethod
523 /*============================= */
524 method Action debug_tdi_i(Bit#(1) debug_tdi);
525 wr_debug_tdi<=debug_tdi;
526 endmethod
527 /*======= Boundary Scan Input Pins ====== */
528 method Action bs_chain_i(Bit#(1) bs_chain);
529 wr_bs_chain_tdo<=bs_chain;
530 endmethod
531 /*======== TAP States ============= */
532 method shift_dr=tapstate==ShiftDR?1:0;
533 method pause_dr=tapstate==PauseDR?1:0;
534 method update_dr=tapstate==UpdateDR?1:0;
535 method capture_dr=tapstate==CaptureDR?1:0;
536 /*=================================== */
537 method debug_select =crossed_instruction==`DEBUG?1:0;
538 /*================================ */
539 /*======= SCAN Output (Scan Chain Inputs) Pins ====== */
540 method scan_in_1 = wr_scan_in_1_all;
541 method scan_in_2 = wr_scan_in_2_out1;
542 method scan_in_3 = wr_scan_in_3_out2;
543 method scan_in_4 = wr_scan_in_4_out3;
544 method scan_in_5 = wr_scan_in_5_out4;
545 method scan_en = scan_en_sr;
546 method scan_mode_te = scan_mode_te_sr;
547 /*======= Boundary Scan Output Pins ====== */
548 method shiftBscan2Edge = shiftBscan2Edge_sr;
549 method selectJtagInput = selectJtagInput_sr;
550 method selectJtagOutput = selectJtagOutput_sr;
551 method updateBscan = updateBscan_sr;
552 method bscan_in = bs_sr;
553 method scan_shift_en = wr_scan_shift_en[1];
554 /*======= JTAG Output Pins ====== */
555 method tdo = crossed_output_tdo;
556 method debug_tdo = wr_tdi;
557 method Bit#(1) tdo_oe = ((tapstate == ShiftIR) || (tapstate == ShiftDR))?1:0;
558 method Action response_from_dm(Bit#(34) responsedm) if(response_from_DM.notFull);
559 if(capture_repsonse_from_dm)
560 response_from_DM.enq(responsedm);
561 endmethod
562 method ActionValue#(Bit#(40)) request_to_dm if(request_to_DM.notEmpty);
563 request_to_DM.deq;
564 return request_to_DM.first;
565 endmethod
566 endmodule
567
568 endpackage
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