src/peripherals/sdram/controller/parallel_prog_delay_cell.v

   1
   2 module parallel_prog_delay_cell ( in_clk, delay_config_reg, delayed_clk);
   3     input in_clk;
   4     input [3:0] delay_config_reg;
   5     output delayed_clk;
   6
   7     wire [7:0] wr_temp_delayed_clk;
   8         wire xor_outp_clk;
   9
  10         xor(xor_outp_clk, delay_config_reg[3], in_clk);
  11
  12         assign wr_temp_delayed_clk[0]= xor_outp_clk;
  13         delay_chain#(3) chain1 (.out(wr_temp_delayed_clk[1]),.in(xor_outp_clk));
  14         delay_chain#(6) chain2 (.out(wr_temp_delayed_clk[2]),.in(xor_outp_clk));
  15         delay_chain#(12) chain3 (.out(wr_temp_delayed_clk[3]),.in(xor_outp_clk));
  16         delay_chain#(18) chain4 (.out(wr_temp_delayed_clk[4]),.in(xor_outp_clk));
  17         delay_chain#(26) chain5 (.out(wr_temp_delayed_clk[5]),.in(xor_outp_clk));
  18         delay_chain#(38) chain6 (.out(wr_temp_delayed_clk[6]),.in(xor_outp_clk));
  19         delay_chain#(50) chain7 (.out(wr_temp_delayed_clk[7]),.in(xor_outp_clk));
  20
  21         assign delayed_clk= wr_temp_delayed_clk[delay_config_reg[2:0]];
  22
  23 endmodule
  24
  25 module delay_chain (in, out);
  26         parameter Depth=0;
  27         input in;
  28         output out;
  29         wire [Depth-1:0] wr_inter;
  30
  31         buf(wr_inter[0],in); // replace this with the buffer from the ASIC library
  32         genvar i;
  33         generate
  34                 for(i=1; i<= Depth-1; i=i+1)
  35                 begin: gen_delay_buffer_chains
  36                         buf(wr_inter[i],wr_inter[i-1]); // replace this with the buffer form the ASIC library.
  37                 end
  38         endgenerate
  39
  40         assign out= wr_inter[Depth-1];
  41 endmodule
  42