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[shakti-peripherals.git] / src / peripherals / sdram / controller / sdrc_core.v
1 /*********************************************************************
2
3 SDRAM Controller Core File
4
5 This file is part of the sdram controller project
6 http://www.opencores.org/cores/sdr_ctrl/
7
8 Description: SDRAM Controller Core Module
9 2 types of SDRAMs are supported, 1Mx16 2 bank, or 4Mx16 4 bank.
10 This block integrate following sub modules
11
12 sdrc_bs_convert
13 convert the system side 32 bit into equvailent 8/16/32 SDR format
14 sdrc_req_gen
15 This module takes requests from the app, chops them to burst booundaries
16 if wrap=0, decodes the bank and passe the request to bank_ctl
17 sdrc_xfr_ctl
18 This module takes requests from sdr_bank_ctl, runs the transfer and
19 controls data flow to/from the app. At the end of the transfer it issues a
20 burst terminate if not at the end of a burst and another command to this
21 bank is not available.
22
23 sdrc_bank_ctl
24 This module takes requests from sdr_req_gen, checks for page hit/miss and
25 issues precharge/activate commands and then passes the request to
26 sdr_xfr_ctl.
27
28
29 Assumption: SDRAM Pads should be placed near to this module. else
30 user should add a FF near the pads
31
32 To Do:
33 nothing
34
35 Author(s):
36 - Dinesh Annayya, dinesha@opencores.org
37 Version : 0.0 - 8th Jan 2012
38 Initial version with 16/32 Bit SDRAM Support
39 : 0.1 - 24th Jan 2012
40 8 Bit SDRAM Support is added
41 0.2 - 2nd Feb 2012
42 Improved the command pipe structure to accept up-to
43 4 command of different bank.
44 0.3 - 7th Feb 2012
45 Bug fix for parameter defination for request length has changed from 9 to 12
46 0.4 - 26th April 2013
47 SDRAM Address Bit is Extended by 12 bit to 13 bit to support higher SDRAM
48
49
50 Copyright (C) 2000 Authors and OPENCORES.ORG
51
52 This source file may be used and distributed without
53 restriction provided that this copyright statement is not
54 removed from the file and that any derivative work contains
55 the original copyright notice and the associated disclaimer.
56
57 This source file is free software; you can redistribute it
58 and/or modify it under the terms of the GNU Lesser General
59 Public License as published by the Free Software Foundation;
60 either version 2.1 of the License, or (at your option) any
61 later version.
62
63 This source is distributed in the hope that it will be
64 useful, but WITHOUT ANY WARRANTY; without even the implied
65 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
66 PURPOSE. See the GNU Lesser General Public License for more
67 details.
68
69 You should have received a copy of the GNU Lesser General
70 Public License along with this source; if not, download it
71 from http://www.opencores.org/lgpl.shtml
72
73 *******************************************************************/
74
75
76
77 module sdrc_core
78 (
79 clk,
80 pad_clk,
81 reset_n,
82 sdr_width,
83 cfg_colbits,
84
85 /* Request from app */
86 app_req, // Transfer Request
87 app_req_addr, // SDRAM Address
88 app_req_len, // Burst Length (in 16 bit words)
89 app_req_wrap, // Wrap mode request (xfr_len = 4)
90 app_req_wr_n, // 0 => Write request, 1 => read req
91 app_req_ack, // Request has been accepted
92 cfg_req_depth, //how many req. buffer should hold
93
94 app_wr_data,
95 app_wr_en_n,
96 app_last_wr,
97
98 app_rd_data,
99 app_rd_valid,
100 app_last_rd,
101 app_wr_next_req,
102 sdr_init_done,
103 app_req_dma_last,
104
105 /* Interface to SDRAMs */
106 sdr_cs_n,
107 sdr_cke,
108 sdr_ras_n,
109 sdr_cas_n,
110 sdr_we_n,
111 sdr_dqm,
112 sdr_ba,
113 sdr_addr,
114 pad_sdr_din,
115 sdr_dout,
116 sdr_den_n,
117
118 /* Parameters */
119 cfg_sdr_en,
120 cfg_sdr_mode_reg,
121 cfg_sdr_tras_d,
122 cfg_sdr_trp_d,
123 cfg_sdr_trcd_d,
124 cfg_sdr_cas,
125 cfg_sdr_trcar_d,
126 cfg_sdr_twr_d,
127 cfg_sdr_rfsh,
128 cfg_sdr_rfmax);
129
130
131 `define SDR_REQ_ID_W 4
132
133 `define SDR_RFSH_TIMER_W 12
134 `define SDR_RFSH_ROW_CNT_W 3
135
136 // B2X Command
137
138 `define OP_PRE 2'b00
139 `define OP_ACT 2'b01
140 `define OP_RD 2'b10
141 `define OP_WR 2'b11
142
143 // SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
144
145 `define SDR_DESEL 4'b1111
146 `define SDR_NOOP 4'b0111
147 `define SDR_ACTIVATE 4'b0011
148 `define SDR_READ 4'b0101
149 `define SDR_WRITE 4'b0100
150 `define SDR_BT 4'b0110
151 `define SDR_PRECHARGE 4'b0010
152 `define SDR_REFRESH 4'b0001
153 `define SDR_MODE 4'b0000
154
155 `define ASIC 1'b1
156 `define FPGA 1'b0
157 `define TARGET_DESIGN `ASIC
158 // 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
159 `define REQ_BW (`TARGET_DESIGN == `FPGA) ? 6 : 12 // Request Width
160
161 parameter APP_AW = 26; // Application Address Width
162 parameter APP_DW = 64; // Application Data Width
163 parameter APP_BW = 8; // Application Byte Width
164 parameter APP_RW = 9; // Application Request Width
165
166 parameter SDR_DW = 64; // SDR Data Width
167 parameter SDR_BW = 8; // SDR Byte Width
168
169
170 //-----------------------------------------------
171 // Global Variable
172 // ----------------------------------------------
173 input clk ; // SDRAM Clock
174 input pad_clk ; // SDRAM Clock from Pad, used for registering Read Data
175 input reset_n ; // Reset Signal
176 input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
177 input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
178
179
180 //------------------------------------------------
181 // Request from app
182 //------------------------------------------------
183 input app_req ; // Application Request
184 input [APP_AW-1:0] app_req_addr ; // Address
185 input app_req_wr_n ; // 0 - Write, 1 - Read
186 input app_req_wrap ; // Address Wrap
187 output app_req_ack ; // Application Request Ack
188
189 input [APP_DW-1:0] app_wr_data ; // Write Data
190 output app_wr_next_req ; // Next Write Data Request
191 input [APP_BW-1:0] app_wr_en_n ; // Byte wise Write Enable
192 output app_last_wr ; // Last Write trannsfer of a given Burst
193 output [APP_DW-1:0] app_rd_data ; // Read Data
194 output app_rd_valid ; // Read Valid
195 output app_last_rd ; // Last Read Transfer of a given Burst
196
197 //------------------------------------------------
198 // Interface to SDRAMs
199 //------------------------------------------------
200 output sdr_cke ; // SDRAM CKE
201 output sdr_cs_n ; // SDRAM Chip Select
202 output sdr_ras_n ; // SDRAM ras
203 output sdr_cas_n ; // SDRAM cas
204 output sdr_we_n ; // SDRAM write enable
205 output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
206 output [1:0] sdr_ba ; // SDRAM Bank Enable
207 output [12:0] sdr_addr ; // SDRAM Address
208 input [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
209 output [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
210 output [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
211
212 //------------------------------------------------
213 // Configuration Parameter
214 //------------------------------------------------
215 output sdr_init_done ; // Indicate SDRAM Initialisation Done
216 input [3:0] cfg_sdr_tras_d ; // Active to precharge delay
217 input [3:0] cfg_sdr_trp_d ; // Precharge to active delay
218 input [3:0] cfg_sdr_trcd_d ; // Active to R/W delay
219 input cfg_sdr_en ; // Enable SDRAM controller
220 input [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller
221 input [APP_RW-1:0] app_req_len ; // Application Burst Request length in 32 bit
222 input [12:0] cfg_sdr_mode_reg ;
223 input [2:0] cfg_sdr_cas ; // SDRAM CAS Latency
224 input [3:0] cfg_sdr_trcar_d ; // Auto-refresh period
225 input [3:0] cfg_sdr_twr_d ; // Write recovery delay
226 input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
227 input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
228 input app_req_dma_last; // this signal should close the bank
229
230 /****************************************************************************/
231 // Internal Nets
232
233 // SDR_REQ_GEN
234 wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
235 wire [1:0] r2b_ba;
236 wire [12:0] r2b_raddr;
237 wire [12:0] r2b_caddr;
238 wire [`REQ_BW-1:0] r2b_len;
239
240 // SDR BANK CTL
241 wire [`SDR_REQ_ID_W-1:0]b2x_id;
242 wire [1:0] b2x_ba;
243 wire [12:0] b2x_addr;
244 wire [`REQ_BW-1:0] b2x_len;
245 wire [1:0] b2x_cmd;
246
247 // SDR_XFR_CTL
248 wire [3:0] x2b_pre_ok;
249 wire [`SDR_REQ_ID_W-1:0]xfr_id;
250 wire [APP_DW-1:0] app_rd_data;
251 wire sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, sdr_we_n;
252 wire [SDR_BW-1:0] sdr_dqm;
253 wire [1:0] sdr_ba;
254 wire [12:0] sdr_addr;
255 wire [SDR_DW-1:0] sdr_dout;
256 wire [SDR_DW-1:0] sdr_dout_int;
257 wire [SDR_BW-1:0] sdr_den_n;
258 wire [SDR_BW-1:0] sdr_den_n_int;
259
260 wire [1:0] xfr_bank_sel;
261
262 wire [APP_AW-1:0] app_req_addr;
263 wire [APP_RW-1:0] app_req_len;
264
265 wire [APP_DW-1:0] app_wr_data;
266 wire [SDR_DW-1:0] a2x_wrdt ;
267 wire [APP_BW-1:0] app_wr_en_n;
268 wire [SDR_BW-1:0] a2x_wren_n;
269
270 //wire [31:0] app_rd_data;
271 wire [SDR_DW-1:0] x2a_rddt;
272
273
274 // synopsys translate_off
275 wire [3:0] sdr_cmd;
276 assign sdr_cmd = {sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n};
277 // synopsys translate_on
278
279 assign sdr_den_n = sdr_den_n_int ;
280 assign sdr_dout = sdr_dout_int ;
281
282
283 // To meet the timing at read path, read data is registered w.r.t pad_sdram_clock and register back to sdram_clk
284 // assumption, pad_sdram_clk is synhronous and delayed clock of sdram_clk.
285 // register w.r.t pad sdram clk
286 reg [SDR_DW-1:0] pad_sdr_din1;
287 reg [SDR_DW-1:0] pad_sdr_din2;
288 always@(posedge pad_clk) begin
289 pad_sdr_din1 <= pad_sdr_din;
290 end
291
292 always@(posedge clk) begin
293 pad_sdr_din2 <= pad_sdr_din1;
294 end
295
296
297 /****************************************************************************/
298 // Instantiate sdr_req_gen
299 // This module takes requests from the app, chops them to burst booundaries
300 // if wrap=0, decodes the bank and passe the request to bank_ctl
301
302 sdrc_req_gen #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_req_gen (
303 .clk (clk ),
304 .reset_n (reset_n ),
305 .cfg_colbits (cfg_colbits ),
306 .sdr_width (sdr_width ),
307
308 /* Req to xfr_ctl */
309 .r2x_idle (r2x_idle ),
310
311 /* Request from app */
312 .req (app_req ),
313 .req_id (4'b0 ),
314 .req_addr (app_req_addr ),
315 .req_len (app_req_len ),
316 .req_wrap (app_req_wrap ),
317 .req_wr_n (app_req_wr_n ),
318 .req_ack (app_req_ack ),
319
320 /* Req to bank_ctl */
321 .r2b_req (r2b_req ),
322 .r2b_req_id (r2b_req_id ),
323 .r2b_start (r2b_start ),
324 .r2b_last (r2b_last ),
325 .r2b_wrap (r2b_wrap ),
326 .r2b_ba (r2b_ba ),
327 .r2b_raddr (r2b_raddr ),
328 .r2b_caddr (r2b_caddr ),
329 .r2b_len (r2b_len ),
330 .r2b_write (r2b_write ),
331 .b2r_ack (b2r_ack ),
332 .b2r_arb_ok (b2r_arb_ok )
333 );
334
335 /****************************************************************************/
336 // Instantiate sdr_bank_ctl
337 // This module takes requests from sdr_req_gen, checks for page hit/miss and
338 // issues precharge/activate commands and then passes the request to
339 // sdr_xfr_ctl.
340
341 sdrc_bank_ctl #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_bank_ctl (
342 .clk (clk ),
343 .reset_n (reset_n ),
344 .a2b_req_depth (cfg_req_depth ),
345
346 /* Req from req_gen */
347 .r2b_req (r2b_req ),
348 .r2b_req_id (r2b_req_id ),
349 .r2b_start (r2b_start ),
350 .r2b_last (r2b_last ),
351 .r2b_wrap (r2b_wrap ),
352 .r2b_ba (r2b_ba ),
353 .r2b_raddr (r2b_raddr ),
354 .r2b_caddr (r2b_caddr ),
355 .r2b_len (r2b_len ),
356 .r2b_write (r2b_write ),
357 .b2r_arb_ok (b2r_arb_ok ),
358 .b2r_ack (b2r_ack ),
359
360 /* Transfer request to xfr_ctl */
361 .b2x_idle (b2x_idle ),
362 .b2x_req (b2x_req ),
363 .b2x_start (b2x_start ),
364 .b2x_last (b2x_last ),
365 .b2x_wrap (b2x_wrap ),
366 .b2x_id (b2x_id ),
367 .b2x_ba (b2x_ba ),
368 .b2x_addr (b2x_addr ),
369 .b2x_len (b2x_len ),
370 .b2x_cmd (b2x_cmd ),
371 .x2b_ack (x2b_ack ),
372
373 /* Status from xfr_ctl */
374 .b2x_tras_ok (b2x_tras_ok ),
375 .x2b_refresh (x2b_refresh ),
376 .x2b_pre_ok (x2b_pre_ok ),
377 .x2b_act_ok (x2b_act_ok ),
378 .x2b_rdok (x2b_rdok ),
379 .x2b_wrok (x2b_wrok ),
380
381 /* for generate cuurent xfr address msb */
382 .sdr_req_norm_dma_last(app_req_dma_last),
383 .xfr_bank_sel (xfr_bank_sel ),
384
385 /* SDRAM Timing */
386 .tras_delay (cfg_sdr_tras_d ),
387 .trp_delay (cfg_sdr_trp_d ),
388 .trcd_delay (cfg_sdr_trcd_d )
389 );
390
391 /****************************************************************************/
392 // Instantiate sdr_xfr_ctl
393 // This module takes requests from sdr_bank_ctl, runs the transfer and
394 // controls data flow to/from the app. At the end of the transfer it issues a
395 // burst terminate if not at the end of a burst and another command to this
396 // bank is not available.
397
398 sdrc_xfr_ctl #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_xfr_ctl (
399 .clk (clk ),
400 .reset_n (reset_n ),
401
402 /* Transfer request from bank_ctl */
403 .r2x_idle (r2x_idle ),
404 .b2x_idle (b2x_idle ),
405 .b2x_req (b2x_req ),
406 .b2x_start (b2x_start ),
407 .b2x_last (b2x_last ),
408 .b2x_wrap (b2x_wrap ),
409 .b2x_id (b2x_id ),
410 .b2x_ba (b2x_ba ),
411 .b2x_addr (b2x_addr ),
412 .b2x_len (b2x_len ),
413 .b2x_cmd (b2x_cmd ),
414 .x2b_ack (x2b_ack ),
415
416 /* Status to bank_ctl, req_gen */
417 .b2x_tras_ok (b2x_tras_ok ),
418 .x2b_refresh (x2b_refresh ),
419 .x2b_pre_ok (x2b_pre_ok ),
420 .x2b_act_ok (x2b_act_ok ),
421 .x2b_rdok (x2b_rdok ),
422 .x2b_wrok (x2b_wrok ),
423
424 /* SDRAM I/O */
425 .sdr_cs_n (sdr_cs_n ),
426 .sdr_cke (sdr_cke ),
427 .sdr_ras_n (sdr_ras_n ),
428 .sdr_cas_n (sdr_cas_n ),
429 .sdr_we_n (sdr_we_n ),
430 .sdr_dqm (sdr_dqm ),
431 .sdr_ba (sdr_ba ),
432 .sdr_addr (sdr_addr ),
433 .sdr_din (pad_sdr_din2 ),
434 .sdr_dout (sdr_dout_int ),
435 .sdr_den_n (sdr_den_n_int ),
436 /* Data Flow to the app */
437 .x2a_rdstart (x2a_rdstart ),
438 .x2a_wrstart (x2a_wrstart ),
439 .x2a_id (xfr_id ),
440 .x2a_rdlast (x2a_rdlast ),
441 .x2a_wrlast (x2a_wrlast ),
442 .a2x_wrdt (a2x_wrdt ),
443 .a2x_wren_n (a2x_wren_n ),
444 .x2a_wrnext (x2a_wrnext ),
445 .x2a_rddt (x2a_rddt ),
446 .x2a_rdok (x2a_rdok ),
447 .sdr_init_done (sdr_init_done ),
448
449 /* SDRAM Parameters */
450 .sdram_enable (cfg_sdr_en ),
451 .sdram_mode_reg (cfg_sdr_mode_reg ),
452
453 /* current xfr bank */
454 .xfr_bank_sel (xfr_bank_sel ),
455
456 /* SDRAM Timing */
457 .cas_latency (cfg_sdr_cas ),
458 .trp_delay (cfg_sdr_trp_d ),
459 .trcar_delay (cfg_sdr_trcar_d ),
460 .twr_delay (cfg_sdr_twr_d ),
461 .rfsh_time (cfg_sdr_rfsh ),
462 .rfsh_rmax (cfg_sdr_rfmax )
463 );
464
465 /****************************************************************************/
466 // Instantiate sdr_bs_convert
467 // This model handle the bus with transaltion from application layer to
468 // 8/16/32 SDRAM Memory format
469 // During Write Phase, this block split the data as per SDRAM Width
470 // During Read Phase, This block does the re-packing based on SDRAM
471 // Width
472 //---------------------------------------------------------------------------
473 sdrc_bs_convert #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_bs_convert (
474 .clk (clk ),
475 .reset_n (reset_n ),
476 .sdr_width (sdr_width ),
477
478 /* Control Signal from xfr ctrl */
479 // Read Interface Inputs
480 .x2a_rdstart (x2a_rdstart ),
481 .x2a_rdlast (x2a_rdlast ),
482 .x2a_rdok (x2a_rdok ),
483 // Read Interface outputs
484 .x2a_rddt (x2a_rddt ),
485
486 // Write Interface, Inputs
487 .x2a_wrstart (x2a_wrstart ),
488 .x2a_wrlast (x2a_wrlast ),
489 .x2a_wrnext (x2a_wrnext ),
490
491 // Write Interface, Outputs
492 .a2x_wrdt (a2x_wrdt ),
493 .a2x_wren_n (a2x_wren_n ),
494
495 /* Control Signal from sdrc_bank_ctl */
496
497 /* Control Signal from/to to application i/f */
498 .app_wr_data (app_wr_data ),
499 .app_wr_en_n (app_wr_en_n ),
500 .app_wr_next (app_wr_next_req ),
501 .app_last_wr (app_last_wr ),
502 .app_rd_data (app_rd_data ),
503 .app_rd_valid (app_rd_valid ),
504 .app_last_rd (app_last_rd )
505
506 );
507
508 endmodule // sdrc_core
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