src/peripherals/sdram/controller/sdrc_top.v

   1 /*********************************************************************
   2
   3   SDRAM Controller top File
   4
   5   This file is part of the sdram controller project
   6   http://www.opencores.org/cores/sdr_ctrl/
   7
   8   Description: SDRAM Controller Top Module.
   9     Support 81/6/32 Bit SDRAM.
  10     Column Address is Programmable
  11     Bank Bit are 2 Bit
  12     Row Bits are 12 Bits
  13
  14     This block integrate following sub modules
  15
  16     sdrc_core
  17         SDRAM Controller file
  18     wb2sdrc
  19         This module transalate the bus protocl from wishbone to custome
  20         sdram controller
  21
  22   To Do:
  23     nothing
  24
  25   Author(s): Dinesh Annayya, dinesha@opencores.org
  26   Version  : 0.0 - 8th Jan 2012
  27                 Initial version with 16/32 Bit SDRAM Support
  28            : 0.1 - 24th Jan 2012
  29                  8 Bit SDRAM Support is added
  30              0.2 - 31st Jan 2012
  31                  sdram_dq and sdram_pad_clk are internally generated
  32              0.3 - 26th April 2013
  33                   Sdram Address witdh is increased from 12 to 13bits
  34
  35
  36  Copyright (C) 2000 Authors and OPENCORES.ORG
  37
  38  This source file may be used and distributed without
  39  restriction provided that this copyright statement is not
  40  removed from the file and that any derivative work contains
  41  the original copyright notice and the associated disclaimer.
  42
  43  This source file is free software; you can redistribute it
  44  and/or modify it under the terms of the GNU Lesser General
  45  Public License as published by the Free Software Foundation;
  46  either version 2.1 of the License, or (at your option) any
  47 later version.
  48
  49  This source is distributed in the hope that it will be
  50  useful, but WITHOUT ANY WARRANTY; without even the implied
  51  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
  52  PURPOSE.  See the GNU Lesser General Public License for more
  53  details.
  54
  55  You should have received a copy of the GNU Lesser General
  56  Public License along with this source; if not, download it
  57  from http://www.opencores.org/lgpl.shtml
  58
  59 *******************************************************************/
  60
  61
  62 `timescale 1ns/1ps
  63 module sdrc_top
  64            (
  65                    cfg_sdr_width       ,
  66                    cfg_colbits         ,
  67
  68                 // Input to sdram ctrl
  69                     app_req        ,
  70                     app_req_addr   ,
  71                     app_req_len    ,
  72                     app_req_wr_n   ,
  73                     app_req_wrap   ,
  74                     app_req_ack    ,
  75 //                  app_busy_n     ,
  76                     app_wr_en_n    ,
  77                     app_wr_next_req,
  78                     app_rd_valid   ,
  79                     app_last_rd    ,
  80                     app_last_wr,
  81                     app_wr_data    ,
  82                     app_rd_data    ,
  83                     delay_config_reg2,
  84
  85                 /* Interface to SDRAMs */
  86                     sdram_clk           ,
  87                     sdram_resetn        ,
  88                     sdr_cs_n            ,
  89                     sdr_cke             ,
  90                     sdr_ras_n           ,
  91                     sdr_cas_n           ,
  92                     sdr_we_n            ,
  93                     sdr_dqm             ,
  94                     sdr_ba              ,
  95                     sdr_addr            ,
  96                     pad_sdr_din         , // SDRA Data Input
  97                     sdr_dout            , // SDRAM Data Output
  98                     sdr_den_n           , // SDRAM Data Output enable
  99
 100                 /* Parameters */
 101                     sdr_init_done       ,
 102                     cfg_req_depth       ,               //how many req. buffer should hold
 103                     cfg_sdr_en          ,
 104                     cfg_sdr_mode_reg    ,
 105                     cfg_sdr_tras_d      ,
 106                     cfg_sdr_trp_d       ,
 107                     cfg_sdr_trcd_d      ,
 108                     cfg_sdr_cas         ,
 109                     cfg_sdr_trcar_d     ,
 110                     cfg_sdr_twr_d       ,
 111                     cfg_sdr_rfsh        ,
 112                     cfg_sdr_rfmax
 113             );
 114
 115   `define SDR_REQ_ID_W       4
 116
 117 `define SDR_RFSH_TIMER_W    12
 118 `define SDR_RFSH_ROW_CNT_W   3
 119
 120 // B2X Command
 121
 122 `define OP_PRE           2'b00
 123 `define OP_ACT           2'b01
 124 `define OP_RD            2'b10
 125 `define OP_WR            2'b11
 126
 127 // SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
 128
 129 `define SDR_DESEL        4'b1111
 130 `define SDR_NOOP         4'b0111
 131 `define SDR_ACTIVATE     4'b0011
 132 `define SDR_READ         4'b0101
 133 `define SDR_WRITE        4'b0100
 134 `define SDR_BT           4'b0110
 135 `define SDR_PRECHARGE    4'b0010
 136 `define SDR_REFRESH      4'b0001
 137 `define SDR_MODE         4'b0000
 138
 139 `define  ASIC            1'b1
 140 `define  FPGA            1'b0
 141 `define  TARGET_DESIGN   `ASIC
 142 // 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
 143 `define  REQ_BW    (`TARGET_DESIGN == `FPGA) ? 6 : 12   //  Request Width
 144
 145 parameter      APP_AW   = 26;  // Application Address Width
 146 parameter      APP_DW   = 64;  // Application Data Width
 147 parameter      APP_BW   = 8;   // Application Byte Width
 148 parameter      APP_RW   = 9;   // Application Request Width
 149
 150 parameter      SDR_DW   = 64;  // SDR Data Width
 151 parameter      SDR_BW   = 8;   // SDR Byte Width
 152
 153 parameter      dw       = 64;  // data width
 154 parameter      tw       = 8;   // tag id width
 155 parameter      bl       = 9;   // burst_lenght_width
 156
 157 //-----------------------------------------------
 158 // Global Variable
 159 // ----------------------------------------------
 160 input                   sdram_clk          ; // SDRAM Clock
 161 input                   sdram_resetn       ; // Reset Signal
 162 input [1:0]             cfg_sdr_width      ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
 163 input [1:0]             cfg_colbits        ; // 2'b00 - 8 Bit column address,
 164                                              // 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
 165
 166 //--------------------------------------
 167 // Wish Bone Interface
 168 // -------------------------------------
 169 //input                   wb_rst_i           ;
 170 //input                   wb_clk_i           ;
 171 //
 172 //input                   wb_stb_i           ;
 173 //output                  wb_ack_o           ;
 174 //input [APP_AW-1:0]            wb_addr_i          ;
 175 //input                   wb_we_i            ; // 1 - Write, 0 - Read
 176 //input [dw-1:0]          wb_dat_i           ;
 177 //input [dw/8-1:0]        wb_sel_i           ; // Byte enable
 178 //output [dw-1:0]         wb_dat_o           ;
 179 //input                   wb_cyc_i           ;
 180 //input  [2:0]            wb_cti_i           ;
 181
 182 //------------------------------------------------
 183 // Interface to SDRAMs
 184 //------------------------------------------------
 185 output                  sdr_cke             ; // SDRAM CKE
 186 output                          sdr_cs_n            ; // SDRAM Chip Select
 187 output                  sdr_ras_n           ; // SDRAM ras
 188 output                  sdr_cas_n           ; // SDRAM cas
 189 output                          sdr_we_n            ; // SDRAM write enable
 190 output [SDR_BW-1:0]     sdr_dqm             ; // SDRAM Data Mask
 191 output [1:0]                sdr_ba              ; // SDRAM Bank Enable
 192 output [12:0]               sdr_addr            ; // SDRAM Address
 193 input [SDR_DW-1:0]          pad_sdr_din         ; // SDRA Data Input
 194 output [SDR_DW-1:0]     sdr_dout            ; // SDRAM Data Output
 195 output [SDR_BW-1:0]     sdr_den_n           ; // SDRAM Data Output enable
 196 //------------------------------------------------
 197 // Configuration Parameter // vis: changed input and output pins to wire
 198 //------------------------------------------------
 199
 200 output                           sdr_init_done       ; // Indicate SDRAM Initialisation Done
 201 input [3:0]                      cfg_sdr_tras_d      ; // Active to precharge delay
 202 input [3:0]                      cfg_sdr_trp_d       ; // Precharge to active delay
 203 input [3:0]                      cfg_sdr_trcd_d      ; // Active to R/W delay
 204 input                                    cfg_sdr_en          ; // Enable SDRAM controller
 205 input [1:0]                          cfg_req_depth       ; // Maximum Request accepted by SDRAM controller
 206 input [12:0]                             cfg_sdr_mode_reg    ;
 207 input [2:0]                              cfg_sdr_cas         ; // SDRAM CAS Latency
 208 input [3:0]                                  cfg_sdr_trcar_d     ; // Auto-refresh period
 209 input [3:0]                      cfg_sdr_twr_d       ; // Write recovery delay
 210 input [`SDR_RFSH_TIMER_W-1 : 0]  cfg_sdr_rfsh;
 211 input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
 212
 213
 214 /*
 215 assign cfg_req_depth  = 2'h3;           //how many req. buffer should hold
 216 assign cfg_sdr_en = 1'b1;
 217 assign cfg_sdr_mode_reg = 13'h033;
 218 assign cfg_sdr_tras_d = 4'h4;
 219 assign cfg_sdr_trp_d = 4'h2;
 220 assign cfg_sdr_trcd_d = 4'h2;
 221 assign cfg_sdr_cas = 3'h3;
 222 assign cfg_sdr_trcar_d = 4'h7;
 223 assign cfg_sdr_twr_d = 4'h1;
 224 assign cfg_sdr_rfsh = 12'h100; // reduced from 12'hC35
 225 assign cfg_sdr_rfmax = 3'h6;*/
 226 //assign cfg_colbits = 2'b00;
 227 //assign cfg_sdr_width = 2'b00;
 228
 229 //--------------------------------------------
 230 // SDRAM controller Interface
 231 //--------------------------------------------
 232 input                  app_req            ; // SDRAM request
 233 input                  app_req_wrap       ; // SDRAM wrap
 234 input [APP_AW-1:0]     app_req_addr       ; // SDRAM Request Address
 235 input [bl-1:0]         app_req_len        ;
 236 input                  app_req_wr_n       ; // 0 - Write, 1 -> Read
 237 output                 app_req_ack        ; // SDRAM request Accepted
 238 wire                   app_busy_n         ; // 0 -> sdr busy
 239 input [dw/8-1:0]       app_wr_en_n        ; // Active low sdr byte-wise write data valid
 240 output                 app_wr_next_req    ; // Ready to accept the next write
 241 output                 app_rd_valid       ; // sdr read valid
 242 output                 app_last_rd        ; // Indicate last Read of Burst Transfer
 243 output                 app_last_wr        ; // Indicate last Write of Burst Transfer
 244 input [dw-1:0]         app_wr_data        ; // sdr write data
 245 output  [dw-1:0]       app_rd_data        ; // sdr read data
 246
 247 input [3:0] delay_config_reg2;
 248
 249 /****************************************
 250 *  These logic has to be implemented using Pads
 251 *  **************************************/
 252 /*wire  [SDR_DW-1:0]    pad_sdr_din         ; // SDRA Data Input
 253 wire  [SDR_DW-1:0]    sdr_dout            ; // SDRAM Data Output
 254 wire  [SDR_BW-1:0]    sdr_den_n           ; // SDRAM Data Output enable
 255 wire [SDR_DW-1:0]         sdr_dq              ; // SDRA Data Input/output*/
 256
 257 /*assign sdr_dq0 = sdr_dq[31:0];
 258 assign sdr_dq1 = sdr_dq[63:32];
 259
 260
 261 assign   sdr_dq = (&sdr_den_n == 1'b0) ? sdr_dout :  {SDR_DW{1'bz}};
 262 assign   pad_sdr_din = {sdr_dq1, sdr_dq0};*/
 263
 264
 265
 266 // sdram pad clock is routed back through pad
 267 // SDRAM Clock from Pad, used for registering Read Data
 268 wire sdram_pad_clk;
 269 parallel_prog_delay_cell delay_inst_for_sdram_clk_pad(.in_clk(sdram_clk), .delay_config_reg(delay_config_reg2), .delayed_clk(sdram_pad_clk));
 270
 271
 272
 273 sdrc_core #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_sdrc_core (
 274           .clk                (sdram_clk          ) ,
 275           .pad_clk            (sdram_pad_clk      ) ,
 276           .reset_n            (sdram_resetn       ) ,
 277           .sdr_width          (cfg_sdr_width      ) ,
 278           .cfg_colbits        (cfg_colbits        ) ,
 279
 280                 /* Request from app */
 281           .app_req            (app_req            ) ,// Transfer Request
 282           .app_req_addr       (app_req_addr       ) ,// SDRAM Address
 283           .app_req_len        (app_req_len        ) ,// Burst Length (in 16 bit words)
 284           .app_req_wrap       (app_req_wrap       ) ,// Wrap mode request
 285           .app_req_wr_n       (app_req_wr_n       ) ,// 0 => Write request, 1 => read req
 286           .app_req_ack        (app_req_ack        ) ,// Request has been accepted
 287           .cfg_req_depth      (cfg_req_depth      ) ,//how many req. buffer should hold
 288
 289           .app_wr_data        (app_wr_data        ) ,
 290           .app_wr_en_n        (app_wr_en_n        ) ,
 291           .app_rd_data        (app_rd_data        ) ,
 292           .app_rd_valid       (app_rd_valid       ) ,
 293                   .app_last_rd        (app_last_rd        ) ,
 294           .app_last_wr        (app_last_wr        ) ,
 295           .app_wr_next_req    (app_wr_next_req    ) ,
 296           .sdr_init_done      (sdr_init_done      ) ,
 297           .app_req_dma_last   (app_req            ) ,
 298
 299                 /* Interface to SDRAMs */
 300           .sdr_cs_n           (sdr_cs_n           ) ,
 301           .sdr_cke            (sdr_cke            ) ,
 302           .sdr_ras_n          (sdr_ras_n          ) ,
 303           .sdr_cas_n          (sdr_cas_n          ) ,
 304           .sdr_we_n           (sdr_we_n           ) ,
 305           .sdr_dqm            (sdr_dqm            ) ,
 306           .sdr_ba             (sdr_ba             ) ,
 307           .sdr_addr           (sdr_addr           ) ,
 308           .pad_sdr_din        (pad_sdr_din        ) ,
 309           .sdr_dout           (sdr_dout           ) ,
 310           .sdr_den_n          (sdr_den_n          ) ,
 311
 312                 /* Parameters */
 313           .cfg_sdr_en         (cfg_sdr_en         ) ,
 314           .cfg_sdr_mode_reg   (cfg_sdr_mode_reg   ) ,
 315           .cfg_sdr_tras_d     (cfg_sdr_tras_d     ) ,
 316           .cfg_sdr_trp_d      (cfg_sdr_trp_d      ) ,
 317           .cfg_sdr_trcd_d     (cfg_sdr_trcd_d     ) ,
 318           .cfg_sdr_cas        (cfg_sdr_cas        ) ,
 319           .cfg_sdr_trcar_d    (cfg_sdr_trcar_d    ) ,
 320           .cfg_sdr_twr_d      (cfg_sdr_twr_d      ) ,
 321           .cfg_sdr_rfsh       (cfg_sdr_rfsh       ) ,
 322           .cfg_sdr_rfmax      (cfg_sdr_rfmax      )
 323                );
 324
 325 endmodule // sdrc_core