src/peripherals/uart/Makefile

   1 ### Makefile for the cclass project
   2
   3 TOP_MODULE:=mkQUART
   4 TOP_FILE:=quart.bsv
   5 TOP_DIR:=./
   6 WORKING_DIR := $(shell pwd)
   7
   8 BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:
   9 BSVINCDIR:= $(BSVINCDIR):../../core
  10 BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4
  11 BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4lite
  12 BSVINCDIR:= $(BSVINCDIR):./test
  13
  14 default: gen_verilog
  15
  16 check-blue:
  17         @if test -z "$$BLUESPECDIR"; then echo "BLUESPECDIR variable not set"; exit 1; fi;
  18
  19 ###### Setting the variables for bluespec compile #$############################
  20 BSVCOMPILEOPTS:= -check-assert -suppress-warnings G0020 -keep-fires -opt-undetermined-vals -remove-false-rules -remove-empty-rules -remove-starved-rules
  21 BSVLINKOPTS:=-parallel-sim-link 8 -keep-fires
  22 VERILOGDIR:=./verilog/
  23 BSVBUILDDIR:=./bsv_build/
  24 BSVOUTDIR:=./bin
  25 ################################################################################
  26
  27 ########## BSIM COMPILE, LINK AND SIMULATE TARGETS ##########################
  28 .PHONY: check-restore
  29 check-restore:
  30         @if [ "$(define_macros)" != "$(old_define_macros)" ];   then    make clean ;    fi;
  31
  32 .PHONY: gen_verilog
  33 gen_verilog: check-restore check-blue
  34         @echo Compiling mkTbSoc in Verilog for simulations ...
  35         @mkdir -p $(BSVBUILDDIR);
  36         @mkdir -p $(VERILOGDIR);
  37         bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) 2>&1 | tee bsv_compile.log
  38         @echo Compilation finished
  39
  40 #############################################################################
  41
  42 .PHONY: clean
  43 clean:
  44         rm -rf $(BSVBUILDDIR) *.log $(BSVOUTDIR) ./bbl*
  45         rm -rf verilog obj_dir bsv_src