add quart wrapper
[shakti-peripherals.git] / src / peripherals / uart / quart.bsv
1 /*
2 Copyright (c) 2013, IIT Madras
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions
7 are met:
8
9 * Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11 * Redistributions in binary form must reproduce the above copyright
12 notice, this list of conditions and the following disclaimer in the
13 documentation and/or other materials provided with the distribution.
14 * Neither the name of IIT Madras nor the names of its contributors
15 may be used to endorse or promote products derived from this software
16 without specific prior written permission.
17
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
25 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
26 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 --------------------------------------------------------------------
30 */
31
32 package quart;
33
34 import AXI4_Lite_Types :: *;
35 import AXI4_Lite_Fabric :: *;
36 import GetPut::*;
37 import Uart16550::*;
38 `include "instance_defines.bsv"
39
40 (*always_ready, always_enabled*)
41 interface QUART_out;
42 interface Put#(Bit#(1)) srx_in;
43 interface Put#(Bit#(1)) cts_in;
44 interface Get#(Bit#(1)) stx_out;
45 interface Get#(Bit#(1)) rts_out;
46 endinterface
47
48 interface QUART_AXI4_Lite_Ifc;
49 interface QUART_out out;
50 interface AXI4_Lite_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) slave;
51 (* always_ready, always_enabled *) method Bit#(1) irq;
52 endinterface
53
54 (*synthesize*)
55 module mkQUART#(Clock core_clock, Reset core_reset)
56 (QUART_AXI4_Lite_Ifc);
57
58 Uart16550_AXI4_Lite_Ifc uart <- mkUart16550(core_clock, core_reset);
59 //uart.pin_dsr_sync <= in;
60 //uart.pin_ri_sync <= in;
61 //uart.pin_dcd_sync <= in;
62 Bit#(1) v1 = 1;
63 Bit#(1) v0 = 1;
64 let dsr_in = uart.coe_rs232.dsr_in.put;
65 dsr_in = v1;
66 let dcd_in = uart.coe_rs232.dcd_in.put;
67 dcd_in = v1;
68 let ri_in = uart.coe_rs232.ri_in.put;
69 ri_in = v0;
70
71 let temp2 <- uart.coe_rs232.dtr_out.get;
72 Bit#(1) temp = temp2;
73 uart.coe_rs232.dtr_out.get(temp);
74
75 interface out = interface QUART_out
76 interface srx_in = interface Put
77 method Action put(Bit#(1) in);
78 uart.coe_rs232.srx_in.put(in); // RX Input
79 endmethod
80 endinterface;
81
82 interface cts_in = interface Put
83 method Action put(Bit#(1) in);
84 uart.coe_rs232.cts_in.put(in); // CTS Input
85 endmethod
86 endinterface;
87
88 interface stx_out = interface Get
89 method ActionValue#(Bit#(1)) get;
90 let temp2 <- uart.coe_rs232.stx_out.get;
91 Bit#(1) temp = temp2;
92 return temp;
93 endmethod
94 endinterface;
95
96 interface rts_out = interface Get
97 method ActionValue#(Bit#(1)) get;
98 let temp2 <- uart.coe_rs232.rts_out.get;
99 Bit#(1) temp = temp2;
100 return temp;
101 endmethod
102 endinterface;
103
104 endinterface;
105
106 interface slave = uart.slave_axi_uart;
107
108 method Bit#(1) irq;
109 return uart.irq;
110 endmethod
111
112 endmodule
113 endpackage