src/uncore/axi4/SlaveWrapper.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package SlaveWrapper;
  15         /*======= Project Imports ====*/
  16         import AXI4_Types::*;
  17         import AXI4_Fabric  :: *;
  18         import AXI4_Lite_Types::*;
  19         import AXI4_Lite_Fabric  :: *;
  20         import Mem_Controller::*;
  21         /*==============================*/
  22
  23         interface SlaveWrapper;
  24                 interface AXI4_Lite_Slave_IFC #(Wd_Addr, Wd_Data, Wd_User) axi4slave;
  25                 interface AXI4_Lite_Master_IFC #(Wd_Addr, Wd_Data, Wd_User) axi4litemaster;
  26         endinterface
  27
  28         module mkSlaveWrapper(SlaveWrapper);
  29    AXI4_Slave_Xactor_IFC #(`Addr_width, `Reg_width, 0)  s_axi4xactor <- mkAXI4_Slave_Xactor;
  30    AXI4_Lite_Master_Xactor_IFC #(`Addr_width, `Reg_width, 0)  m_axi4litexactor <- mkAXI4_Lite_Slave_Xactor;
  31
  32          Reg#(Bit#(8)) rg_readburst_counter<-mkReg(0);
  33          Reg#(Bit#(8)) rg_readburst_value<-mkReg(0);
  34          Reg#(Bit#(8)) rg_writeburst_counter<-mkReg(0);
  35          Reg#(Bit#(8)) rg_writeburst_value<-mkReg(0);
  36
  37    rule rl_wr_request;
  38       // Get the wr request
  39       let awreq <- pop_o (s_xactor.o_wr_addr);
  40       let wreq  <- pop_o (s_xactor.o_wr_data);
  41       let aw = AXI4_Lite_Wr_Addr {awaddr: awreq.awaddr, awprot:awreq.awprot, awuser:0};
  42       let w  = AXI4_Lite_Wr_Data {wdata:  wreq.wdata, wstrb: wreq.wstrb,};
  43       m_axi4litexactor.i_wr_addr.enq(aw);
  44       m_axi4litexactor.i_wr_data.enq(w);
  45                         rg_writeburst_value<=awreq.awlen;
  46                 endrule
  47
  48                 rule rl_wr_response;
  49                         let axi4lite_wr_response<-pop_o(m_axi4litexactor.o_wr_resp);
  50             let b = AXI4_Wr_Resp {bresp: axi4lite_wr_response.bresp, buser: axi4lite_wr_response.buser};
  51                         if(rg_writeburst_counter==rg_writeburst_value)begin
  52                                 rg_writeburst_counter<=0;
  53         s_axi4xactor.i_wr_resp.enq (b);
  54                         end
  55                         else
  56                                 rg_writeburst_counter<=rg_writeburst_counter+1;
  57                         `ifdef verbose $display($time,"\t",module_name,":\t Recieved Write Request for Address: %h data: %h strb: %b awlen: %d rg_writeburst_counter: %d",aw.awaddr,w.wdata,w.wstrb,aw.awlen,rg_writeburst_counter);  `endif
  58    endrule
  59
  60         endmodule
  61
  62 endpackage