Merge remote-tracking branch 'origin/master' into typed_pad_ctrl
[sifive-blocks.git] / src / main / scala / devices / gpio / GPIOPeriphery.scala
1 // See LICENSE for license details.
2 package sifive.blocks.devices.gpio
3
4 import Chisel._
5 import freechips.rocketchip.config.Field
6 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
7 import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
8 import freechips.rocketchip.util.HeterogeneousBag
9
10 case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
11
12 trait HasPeripheryGPIO extends HasPeripheryBus with HasInterruptBus {
13 val gpioParams = p(PeripheryGPIOKey)
14 val gpios = gpioParams map { params =>
15 val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params))
16 gpio.node := pbus.toVariableWidthSlaves
17 ibus.fromSync := gpio.intnode
18 gpio
19 }
20 }
21
22 trait HasPeripheryGPIOBundle {
23 val gpio: HeterogeneousBag[GPIOPortIO]
24 }
25
26 trait HasPeripheryGPIOModuleImp extends LazyMultiIOModuleImp with HasPeripheryGPIOBundle {
27 val outer: HasPeripheryGPIO
28 val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_))))
29
30 (gpio zip outer.gpios) foreach { case (io, device) =>
31 io <> device.module.io.port
32 }
33 }