src/main/scala/devices/pwm/PWM.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.pwm
   3
   4 import Chisel._
   5 import chisel3.experimental.MultiIOModule
   6 import Chisel.ImplicitConversions._
   7 import freechips.rocketchip.config.Parameters
   8 import freechips.rocketchip.regmapper._
   9 import freechips.rocketchip.tilelink._
  10 import freechips.rocketchip.util._
  11 import sifive.blocks.util.GenericTimer
  12
  13 // Core PWM Functionality  & Register Interface
  14
  15 class PWM(val ncmp: Int = 4, val cmpWidth: Int = 16) extends GenericTimer {
  16   protected def countWidth = ((1 << scaleWidth) - 1) + cmpWidth
  17   protected lazy val countAlways = RegEnable(io.regs.cfg.write.bits(12), Bool(false), io.regs.cfg.write.valid && unlocked)
  18   protected lazy val feed = count.carryOut(scale + UInt(cmpWidth))
  19   protected lazy val countEn = Wire(Bool())
  20   override protected lazy val oneShot = RegEnable(io.regs.cfg.write.bits(13) && !countReset, Bool(false), (io.regs.cfg.write.valid && unlocked) || countReset)
  21   override protected lazy val center = RegEnable(io.regs.cfg.write.bits(16 + ncmp - 1, 16), io.regs.cfg.write.valid && unlocked)
  22   override protected lazy val gang = RegEnable(io.regs.cfg.write.bits(24 + ncmp - 1, 24), io.regs.cfg.write.valid && unlocked)
  23   override protected lazy val deglitch = RegEnable(io.regs.cfg.write.bits(10), io.regs.cfg.write.valid && unlocked)(0)
  24   override protected lazy val sticky = RegEnable(io.regs.cfg.write.bits(8), io.regs.cfg.write.valid && unlocked)(0)
  25   override protected lazy val ip = {
  26     val doSticky = Reg(next = (deglitch && !countReset) || sticky)
  27     val sel = ((0 until ncmp).map(i => s(cmpWidth-1) && center(i))).asUInt
  28     val reg = Reg(UInt(width = ncmp))
  29     reg := (sel & elapsed.asUInt) | (~sel & (elapsed.asUInt | (Fill(ncmp, doSticky) & reg)))
  30     when (io.regs.cfg.write.valid && unlocked) { reg := io.regs.cfg.write.bits(28 + ncmp - 1, 28) }
  31     reg
  32   }
  33   lazy val io = new GenericTimerIO {
  34     val gpio = Vec(ncmp, Bool()).asOutput
  35   }
  36   io.gpio := io.gpio.fromBits(ip & ~(gang & Cat(ip(0), ip >> 1)))
  37   countEn := countAlways || oneShot
  38 }
  39
  40 case class PWMParams(
  41   address: BigInt,
  42   size: Int = 0x1000,
  43   regBytes: Int = 4,
  44   ncmp: Int = 4,
  45   cmpWidth: Int = 16)
  46
  47 trait HasPWMBundleContents extends Bundle {
  48   def params: PWMParams
  49   val gpio = Vec(params.ncmp, Bool()).asOutput
  50 }
  51
  52 trait HasPWMModuleContents extends MultiIOModule with HasRegMap {
  53   val io: HasPWMBundleContents
  54   val params: PWMParams
  55
  56   val pwm = Module(new PWM(params.ncmp, params.cmpWidth))
  57
  58   interrupts := pwm.io.ip
  59   io.gpio := pwm.io.gpio
  60
  61   regmap((GenericTimer.timerRegMap(pwm, 0, params.regBytes)):_*)
  62 }
  63
  64 class TLPWM(w: Int, c: PWMParams)(implicit p: Parameters)
  65   extends TLRegisterRouter(c.address, "pwm", Seq("sifive,pwm0"), interrupts = c.ncmp, size = c.size, beatBytes = w)(
  66   new TLRegBundle(c, _)    with HasPWMBundleContents)(
  67   new TLRegModule(c, _, _) with HasPWMModuleContents)