src/main/scala/devices/pwm/PWMPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.pwm
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
   7 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
   8 import freechips.rocketchip.util.HeterogeneousBag
   9 import sifive.blocks.devices.pinctrl.{Pin}
  10
  11 class PWMPortIO(val c: PWMParams) extends Bundle {
  12   val port = Vec(c.ncmp, Bool()).asOutput
  13   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
  14 }
  15
  16 class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle {
  17
  18   val pwm: Vec[T] = Vec(c.ncmp, pingen())
  19
  20   override def cloneType: this.type =
  21     this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
  22 }
  23
  24
  25 class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends PWMSignals[T](pingen, c) {
  26
  27   override def cloneType: this.type =
  28     this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
  29
  30   def fromPort(port: PWMPortIO) {
  31     (pwm zip port.port)  foreach {case (pin, port) =>
  32       pin.outputPin(port)
  33     }
  34   }
  35 }
  36
  37 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
  38
  39 trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus {
  40   val pwmParams = p(PeripheryPWMKey)
  41   val pwms = pwmParams map { params =>
  42     val pwm = LazyModule(new TLPWM(pbus.beatBytes, params))
  43     pwm.node := pbus.toVariableWidthSlaves
  44     ibus.fromSync := pwm.intnode
  45     pwm
  46   }
  47 }
  48
  49 trait HasPeripheryPWMBundle {
  50   val pwm: HeterogeneousBag[PWMPortIO]
  51
  52 }
  53
  54 trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
  55   val outer: HasPeripheryPWM
  56   val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
  57
  58   (pwm zip outer.pwms) foreach { case (io, device) =>
  59     io.port := device.module.io.gpio
  60   }
  61 }