src/main/scala/devices/pwm/PWMPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.pwm
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
   7 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
   8 import freechips.rocketchip.util.HeterogeneousBag
   9 import sifive.blocks.devices.pinctrl.{Pin}
  10
  11 class PWMPortIO(val c: PWMParams) extends Bundle {
  12   val port = Vec(c.ncmp, Bool()).asOutput
  13   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
  14 }
  15
  16 class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
  17
  18   val pwm: Vec[T] = Vec(c.ncmp, pingen())
  19
  20   override def cloneType: this.type =
  21     this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
  22
  23   def fromPWMPort(port: PWMPortIO) {
  24     (pwm zip port.port)  foreach {case (pin, port) =>
  25       pin.outputPin(port)
  26     }
  27   }
  28 }
  29
  30 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
  31
  32 trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus {
  33   val pwmParams = p(PeripheryPWMKey)
  34   val pwms = pwmParams map { params =>
  35     val pwm = LazyModule(new TLPWM(pbus.beatBytes, params))
  36     pwm.node := pbus.toVariableWidthSlaves
  37     ibus.fromSync := pwm.intnode
  38     pwm
  39   }
  40 }
  41
  42 trait HasPeripheryPWMBundle {
  43   val pwm: HeterogeneousBag[PWMPortIO]
  44
  45 }
  46
  47 trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
  48   val outer: HasPeripheryPWM
  49   val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
  50
  51   (pwm zip outer.pwms) foreach { case (io, device) =>
  52     io.port := device.module.io.gpio
  53   }
  54 }