src/main/scala/devices/pwm/PWMPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.pwm
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
   7 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
   8 import freechips.rocketchip.util.HeterogeneousBag
   9 import sifive.blocks.devices.gpio._
  10
  11 class PWMPortIO(val c: PWMParams) extends Bundle {
  12   val port = Vec(c.ncmp, Bool()).asOutput
  13   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
  14 }
  15
  16 class PWMPinsIO(val c: PWMParams) extends Bundle {
  17   val pwm = Vec(c.ncmp, new GPIOPin)
  18 }
  19
  20 class PWMGPIOPort(val c: PWMParams) extends Module {
  21   val io = new Bundle {
  22     val pwm = new PWMPortIO(c).flip()
  23     val pins = new PWMPinsIO(c)
  24   }
  25
  26   GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
  27 }
  28
  29 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
  30
  31 trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus {
  32   val pwmParams = p(PeripheryPWMKey)
  33   val pwms = pwmParams map { params =>
  34     val pwm = LazyModule(new TLPWM(pbus.beatBytes, params))
  35     pwm.node := pbus.toVariableWidthSlaves
  36     ibus.fromSync := pwm.intnode
  37     pwm
  38   }
  39 }
  40
  41 trait HasPeripheryPWMBundle {
  42   val pwms: HeterogeneousBag[PWMPortIO]
  43
  44   def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMPinsIO] = pwms.map { p =>
  45     val pins = Module(new PWMGPIOPort(p.c))
  46     pins.io.pwm <> p
  47     pins.io.pins
  48   }
  49 }
  50
  51 trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
  52   val outer: HasPeripheryPWM
  53   val pwms = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
  54
  55   (pwms zip outer.pwms) foreach { case (io, device) =>
  56     io.port := device.module.io.gpio
  57   }
  58 }