src/main/scala/devices/spi/SPIPins.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.spi
   3
   4 import Chisel._
   5 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
   6
   7 class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
   8
   9   val sck: T      = pingen()
  10   val dq: Vec[T]  = Vec(4, pingen())
  11   val cs: Vec[T]  = Vec(c.csWidth, pingen())
  12
  13   def fromSPIPort(spi: SPIPortIO, syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
  14
  15     sck.outputPin(spi.sck, ds = driveStrength)
  16
  17     (dq zip spi.dq).foreach {case (p, s) =>
  18       p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
  19       p.o.oe := s.oe
  20       p.o.ie := ~s.oe
  21       s.i := ShiftRegister(p.i.ival, syncStages)
  22     }
  23
  24     (cs zip spi.cs) foreach { case (c, s) =>
  25       c.outputPin(s, ds = driveStrength)
  26     }
  27   }
  28 }