src/main/scala/devices/spi/TLSPIFlash.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.spi
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Parameters
   6 import freechips.rocketchip.diplomacy._
   7 import freechips.rocketchip.regmapper._
   8 import freechips.rocketchip.tilelink._
   9 import freechips.rocketchip.util.HeterogeneousBag
  10
  11 trait SPIFlashParamsBase extends SPIParamsBase {
  12   val fAddress: BigInt
  13   val fSize: BigInt
  14   val fBufferDepth: Int
  15
  16   val insnAddrBytes: Int
  17   val insnPadLenBits: Int
  18   lazy val insnCmdBits = frameBits
  19   lazy val insnAddrBits = insnAddrBytes * frameBits
  20   lazy val insnAddrLenBits = log2Floor(insnAddrBytes) + 1
  21 }
  22
  23 case class SPIFlashParams(
  24     rAddress: BigInt,
  25     fAddress: BigInt,
  26     fBufferDepth: Int = 0,
  27     rSize: BigInt = 0x1000,
  28     fSize: BigInt = 0x20000000,
  29     rxDepth: Int = 8,
  30     txDepth: Int = 8,
  31     csWidth: Int = 1,
  32     delayBits: Int = 8,
  33     divisorBits: Int = 12,
  34     sampleDelay: Int = 2)
  35   extends SPIFlashParamsBase {
  36   val frameBits = 8
  37   val insnAddrBytes = 4
  38   val insnPadLenBits = 4
  39
  40   require(insnPadLenBits <= delayBits)
  41   require(sampleDelay >= 0)
  42 }
  43
  44 class SPIFlashTopModule(c: SPIFlashParamsBase, outer: TLSPIFlashBase)
  45   extends SPITopModule(c, outer) {
  46
  47   val flash = Module(new SPIFlashMap(c))
  48   val arb = Module(new SPIArbiter(c, 2))
  49
  50   private val (f, _) = outer.fnode.in(0)
  51   // Tie unused channels
  52   f.b.valid := Bool(false)
  53   f.c.ready := Bool(true)
  54   f.e.ready := Bool(true)
  55
  56   val a = Reg(f.a.bits)
  57   val a_msb = log2Ceil(c.fSize) - 1
  58
  59   when (f.a.fire()) {
  60     a := f.a.bits
  61   }
  62
  63   flash.io.addr.bits.next := f.a.bits.address(a_msb, 0)
  64   flash.io.addr.bits.hold := a.address(a_msb, 0)
  65   flash.io.addr.valid := f.a.valid
  66   f.a.ready := flash.io.addr.ready
  67
  68   f.d.bits := outer.fnode.edges.in.head.AccessAck(a, flash.io.data.bits)
  69   f.d.valid := flash.io.data.valid
  70   flash.io.data.ready := f.d.ready
  71
  72   val insn = Reg(init = SPIFlashInsn.init(c))
  73   val flash_en = Reg(init = Bool(true))
  74
  75   flash.io.ctrl.insn := insn
  76   flash.io.ctrl.fmt <> ctrl.fmt
  77   flash.io.en := flash_en
  78   arb.io.sel := !flash_en
  79
  80   protected val regmapFlash = Seq(
  81     SPICRs.insnmode -> Seq(RegField(1, flash_en)),
  82     SPICRs.insnfmt -> Seq(
  83       RegField(1, insn.cmd.en),
  84       RegField(c.insnAddrLenBits, insn.addr.len),
  85       RegField(c.insnPadLenBits, insn.pad.cnt)),
  86     SPICRs.insnproto -> Seq(
  87       RegField(SPIProtocol.width, insn.cmd.proto),
  88       RegField(SPIProtocol.width, insn.addr.proto),
  89       RegField(SPIProtocol.width, insn.data.proto)),
  90     SPICRs.insncmd -> Seq(RegField(c.insnCmdBits, insn.cmd.code)),
  91     SPICRs.insnpad -> Seq(RegField(c.frameBits, insn.pad.code)))
  92 }
  93
  94 abstract class TLSPIFlashBase(w: Int, c: SPIFlashParamsBase)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {
  95   require(isPow2(c.fSize))
  96   val fnode = TLManagerNode(Seq(TLManagerPortParameters(
  97     managers = Seq(TLManagerParameters(
  98       address     = Seq(AddressSet(c.fAddress, c.fSize-1)),
  99       resources   = device.reg("mem"),
 100       regionType  = RegionType.UNCACHED,
 101       executable  = true,
 102       supportsGet = TransferSizes(1, 1),
 103       fifoId      = Some(0))),
 104     beatBytes = 1)))
 105 }
 106
 107 class TLSPIFlash(w: Int, c: SPIFlashParams)(implicit p: Parameters) extends TLSPIFlashBase(w,c)(p) {
 108   lazy val module = new SPIFlashTopModule(c, this) {
 109
 110     arb.io.inner(0) <> flash.io.link
 111     arb.io.inner(1) <> fifo.io.link
 112     mac.io.link <> arb.io.outer
 113
 114     rnode.regmap(regmapBase ++ regmapFlash:_*)
 115   }
 116 }