src/main/scala/devices/uart/UARTPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.uart
   3
   4 import Chisel._
   5 import chisel3.experimental.{withClockAndReset}
   6 import freechips.rocketchip.config.Field
   7 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
   8 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
   9 import sifive.blocks.devices.pinctrl.{Pin}
  10 import sifive.blocks.util.ShiftRegisterInit
  11
  12 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
  13
  14 trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
  15   val uartParams = p(PeripheryUARTKey)
  16   val uarts = uartParams map { params =>
  17     val uart = LazyModule(new TLUART(pbus.beatBytes, params))
  18     uart.node := pbus.toVariableWidthSlaves
  19     ibus.fromSync := uart.intnode
  20     uart
  21   }
  22 }
  23
  24 trait HasPeripheryUARTBundle {
  25   val uart: Vec[UARTPortIO]
  26
  27   def tieoffUARTs(dummy: Int = 1) {
  28     uart.foreach { _.rxd := UInt(1) }
  29   }
  30
  31 }
  32
  33 trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
  34   val outer: HasPeripheryUART
  35   val uart = IO(Vec(outer.uartParams.size, new UARTPortIO))
  36
  37   (uart zip outer.uarts).foreach { case (io, device) =>
  38     io <> device.module.io.port
  39   }
  40 }
  41
  42 class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
  43   val rxd = pingen()
  44   val txd = pingen()
  45
  46   override def cloneType: this.type =
  47     this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
  48
  49   def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
  50     withClockAndReset(clock, reset) {
  51       txd.outputPin(uart.txd)
  52       val rxd_t = rxd.inputPin()
  53       uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
  54     }
  55   }
  56 }
  57