src/main/scala/devices/uart/UARTPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.uart
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
   7 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
   8 import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
   9 import sifive.blocks.util.ShiftRegisterInit
  10
  11 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
  12
  13 trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
  14   val uartParams = p(PeripheryUARTKey)
  15   val divinit = (p(PeripheryBusParams).frequency / 115200).toInt
  16   val uarts = uartParams map { params =>
  17     val uart = LazyModule(new TLUART(pbus.beatBytes, params.copy(divisorInit = divinit)))
  18     uart.node := pbus.toVariableWidthSlaves
  19     ibus.fromSync := uart.intnode
  20     uart
  21   }
  22 }
  23
  24 trait HasPeripheryUARTBundle {
  25   val uarts: Vec[UARTPortIO]
  26
  27   def tieoffUARTs(dummy: Int = 1) {
  28     uarts.foreach { _.rxd := UInt(1) }
  29   }
  30
  31   def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
  32     val pins = Module(new UARTGPIOPort(syncStages))
  33     pins.io.uart <> u
  34     pins.io.pins
  35   }
  36 }
  37
  38 trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
  39   val outer: HasPeripheryUART
  40   val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO))
  41
  42   (uarts zip outer.uarts).foreach { case (io, device) =>
  43     io <> device.module.io.port
  44   }
  45 }
  46
  47 class UARTPinsIO extends Bundle {
  48   val rxd = new GPIOPin
  49   val txd = new GPIOPin
  50 }
  51
  52 class UARTGPIOPort(syncStages: Int = 0) extends Module {
  53   val io = new Bundle{
  54     val uart = new UARTPortIO().flip()
  55     val pins = new UARTPinsIO
  56   }
  57
  58   GPIOOutputPinCtrl(io.pins.txd, io.uart.txd)
  59   val rxd = GPIOInputPinCtrl(io.pins.rxd)
  60   io.uart.rxd := ShiftRegisterInit(rxd, syncStages, Bool(true))
  61 }