src/main/scala/devices/uart/UARTPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.uart
   3
   4 import Chisel._
   5 import config._
   6 import diplomacy._
   7 import uncore.tilelink2._
   8 import rocketchip._
   9
  10 import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
  11 import sifive.blocks.util.ShiftRegisterInit
  12
  13 trait PeripheryUART {
  14   this: TopNetwork {
  15     val uartConfigs: Seq[UARTConfig]
  16   } =>
  17   val uartDevices = uartConfigs.zipWithIndex.map { case (c, i) =>
  18     val uart = LazyModule(new UART(c) { override lazy val valName = Some(s"uart$i") } )
  19     uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
  20     intBus.intnode := uart.intnode
  21     uart
  22   }
  23 }
  24
  25 trait PeripheryUARTBundle {
  26   this: { val uartConfigs: Seq[UARTConfig] } =>
  27   val uarts = Vec(uartConfigs.size, new UARTPortIO)
  28 }
  29
  30 trait PeripheryUARTModule {
  31   this: TopNetworkModule {
  32     val outer: PeripheryUART
  33     val io: PeripheryUARTBundle
  34   } =>
  35   (io.uarts zip outer.uartDevices).foreach { case (io, device) =>
  36     io <> device.module.io.port
  37   }
  38 }
  39
  40 class UARTPinsIO extends Bundle {
  41   val rxd = new GPIOPin
  42   val txd = new GPIOPin
  43 }
  44
  45 class UARTGPIOPort(syncStages: Int = 0) extends Module {
  46   val io = new Bundle{
  47     val uart = new UARTPortIO().flip()
  48     val pins = new UARTPinsIO
  49   }
  50
  51   GPIOOutputPinCtrl(io.pins.txd, io.uart.txd)
  52   val rxd = GPIOInputPinCtrl(io.pins.rxd)
  53   io.uart.rxd := ShiftRegisterInit(rxd, syncStages, Bool(true))
  54 }