src/main/scala/devices/uart/UARTPins.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.uart
   3
   4 import Chisel._
   5 import chisel3.experimental.{withClockAndReset}
   6 import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
   7 import sifive.blocks.devices.pinctrl.{Pin}
   8
   9 class UARTSignals[T <: Data](private val pingen: () => T) extends Bundle {
  10   val rxd = pingen()
  11   val txd = pingen()
  12 }
  13
  14 class UARTPins[T <: Pin](pingen: () => T) extends UARTSignals[T](pingen)
  15
  16 object UARTPinsFromPort {
  17   def apply[T <: Pin](pins: UARTSignals[T], uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
  18     withClockAndReset(clock, reset) {
  19       pins.txd.outputPin(uart.txd)
  20       val rxd_t = pins.rxd.inputPin()
  21       uart.rxd := SyncResetSynchronizerShiftReg(rxd_t, syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
  22     }
  23   }
  24 }
  25