src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707mig
   3
   4 import Chisel._
   5 import config._
   6 import diplomacy._
   7 import uncore.tilelink2._
   8 import uncore.axi4._
   9 import rocketchip._
  10 import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGUnidirectionalIOClocksReset, VC707MIGUnidirectionalIODDR, vc707mig}
  11
  12 trait HasXilinxVC707MIGParameters {
  13 }
  14
  15 class XilinxVC707MIGPads extends Bundle with VC707MIGUnidirectionalIODDR {
  16   val _inout_ddr3_dq = Bits(OUTPUT,64)
  17   val _inout_ddr3_dqs_n = Bits(OUTPUT,8)
  18   val _inout_ddr3_dqs_p = Bits(OUTPUT,8)
  19 }
  20
  21 class XilinxVC707MIGIO extends Bundle with VC707MIGUnidirectionalIODDR
  22                                       with VC707MIGUnidirectionalIOClocksReset {
  23   val _inout_ddr3_dq = Bits(OUTPUT,64)
  24   val _inout_ddr3_dqs_n = Bits(OUTPUT,8)
  25   val _inout_ddr3_dqs_p = Bits(OUTPUT,8)
  26 }
  27
  28 class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
  29   val device = new MemoryDevice
  30   val node = TLInputNode()
  31   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
  32     slaves = Seq(AXI4SlaveParameters(
  33       address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
  34       resources     = device.reg,
  35       regionType    = RegionType.UNCACHED,
  36       executable    = true,
  37       supportsWrite = TransferSizes(1, 256*8),
  38       supportsRead  = TransferSizes(1, 256*8),
  39       interleavedId = Some(0))),
  40     beatBytes = 8)))
  41
  42   val xing = LazyModule(new TLAsyncCrossing)
  43   val toaxi4 = LazyModule(new TLToAXI4(idBits = 4))
  44
  45   xing.node := node
  46   val monitor = (toaxi4.node := xing.node)
  47   axi4 := toaxi4.node
  48
  49   lazy val module = new LazyModuleImp(this) {
  50     val io = new Bundle {
  51       val port = new XilinxVC707MIGIO
  52       val tl = node.bundleIn
  53     }
  54
  55     //MIG black box instantiation
  56     val blackbox = Module(new vc707mig)
  57
  58     //pins to top level
  59
  60     //inouts
  61     io.port._inout_ddr3_dq    := blackbox.io.ddr3_dq
  62     io.port._inout_ddr3_dqs_n := blackbox.io.ddr3_dqs_n
  63     io.port._inout_ddr3_dqs_p := blackbox.io.ddr3_dqs_p
  64
  65     //outputs
  66     io.port.ddr3_addr         := blackbox.io.ddr3_addr
  67     io.port.ddr3_ba           := blackbox.io.ddr3_ba
  68     io.port.ddr3_ras_n        := blackbox.io.ddr3_ras_n
  69     io.port.ddr3_cas_n        := blackbox.io.ddr3_cas_n
  70     io.port.ddr3_we_n         := blackbox.io.ddr3_we_n
  71     io.port.ddr3_reset_n      := blackbox.io.ddr3_reset_n
  72     io.port.ddr3_ck_p         := blackbox.io.ddr3_ck_p
  73     io.port.ddr3_ck_n         := blackbox.io.ddr3_ck_n
  74     io.port.ddr3_cke          := blackbox.io.ddr3_cke
  75     io.port.ddr3_cs_n         := blackbox.io.ddr3_cs_n
  76     io.port.ddr3_dm           := blackbox.io.ddr3_dm
  77     io.port.ddr3_odt          := blackbox.io.ddr3_odt
  78
  79     //inputs
  80     //differential system clock
  81     blackbox.io.sys_clk_n     := io.port.sys_clk_n
  82     blackbox.io.sys_clk_p     := io.port.sys_clk_p
  83
  84     //user interface signals
  85     val axi_async = axi4.bundleIn(0)
  86     xing.module.io.in_clock := clock
  87     xing.module.io.in_reset := reset
  88     xing.module.io.out_clock := blackbox.io.ui_clk
  89     xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
  90     toaxi4.module.clock := blackbox.io.ui_clk
  91     toaxi4.module.reset := blackbox.io.ui_clk_sync_rst
  92     monitor.foreach { lm =>
  93       lm.module.clock := blackbox.io.ui_clk
  94       lm.module.reset := blackbox.io.ui_clk_sync_rst
  95     }
  96
  97     io.port.ui_clk            := blackbox.io.ui_clk
  98     io.port.ui_clk_sync_rst   := blackbox.io.ui_clk_sync_rst
  99     io.port.mmcm_locked       := blackbox.io.mmcm_locked
 100     blackbox.io.aresetn       := io.port.aresetn
 101     blackbox.io.app_sr_req    := Bool(false)
 102     blackbox.io.app_ref_req   := Bool(false)
 103     blackbox.io.app_zq_req    := Bool(false)
 104     //app_sr_active           := unconnected
 105     //app_ref_ack             := unconnected
 106     //app_zq_ack              := unconnected
 107
 108     //slave AXI interface write address ports
 109     blackbox.io.s_axi_awid    := axi_async.aw.bits.id
 110     blackbox.io.s_axi_awaddr  := axi_async.aw.bits.addr //truncation ??
 111     blackbox.io.s_axi_awlen   := axi_async.aw.bits.len
 112     blackbox.io.s_axi_awsize  := axi_async.aw.bits.size
 113     blackbox.io.s_axi_awburst := axi_async.aw.bits.burst
 114     blackbox.io.s_axi_awlock  := axi_async.aw.bits.lock
 115     blackbox.io.s_axi_awcache := UInt("b0011")
 116     blackbox.io.s_axi_awprot  := axi_async.aw.bits.prot
 117     blackbox.io.s_axi_awqos   := axi_async.aw.bits.qos
 118     blackbox.io.s_axi_awvalid := axi_async.aw.valid
 119     axi_async.aw.ready        := blackbox.io.s_axi_awready
 120
 121     //slave interface write data ports
 122     blackbox.io.s_axi_wdata   := axi_async.w.bits.data
 123     blackbox.io.s_axi_wstrb   := axi_async.w.bits.strb
 124     blackbox.io.s_axi_wlast   := axi_async.w.bits.last
 125     blackbox.io.s_axi_wvalid  := axi_async.w.valid
 126     axi_async.w.ready         := blackbox.io.s_axi_wready
 127
 128     //slave interface write response
 129     blackbox.io.s_axi_bready  := axi_async.b.ready
 130     axi_async.b.bits.id       := blackbox.io.s_axi_bid
 131     axi_async.b.bits.resp     := blackbox.io.s_axi_bresp
 132     axi_async.b.valid         := blackbox.io.s_axi_bvalid
 133
 134     //slave AXI interface read address ports
 135     blackbox.io.s_axi_arid    := axi_async.ar.bits.id
 136     blackbox.io.s_axi_araddr  := axi_async.ar.bits.addr //truncation ??
 137     blackbox.io.s_axi_arlen   := axi_async.ar.bits.len
 138     blackbox.io.s_axi_arsize  := axi_async.ar.bits.size
 139     blackbox.io.s_axi_arburst := axi_async.ar.bits.burst
 140     blackbox.io.s_axi_arlock  := axi_async.ar.bits.lock
 141     blackbox.io.s_axi_arcache := UInt("b0011")
 142     blackbox.io.s_axi_arprot  := axi_async.ar.bits.prot
 143     blackbox.io.s_axi_arqos   := axi_async.ar.bits.qos
 144     blackbox.io.s_axi_arvalid := axi_async.ar.valid
 145     axi_async.ar.ready        := blackbox.io.s_axi_arready
 146
 147     //slace AXI interface read data ports
 148     blackbox.io.s_axi_rready  := axi_async.r.ready
 149     axi_async.r.bits.id       := blackbox.io.s_axi_rid
 150     axi_async.r.bits.data     := blackbox.io.s_axi_rdata
 151     axi_async.r.bits.resp     := blackbox.io.s_axi_rresp
 152     axi_async.r.bits.last     := blackbox.io.s_axi_rlast
 153     axi_async.r.valid         := blackbox.io.s_axi_rvalid
 154
 155     //misc
 156     io.port.init_calib_complete := blackbox.io.init_calib_complete
 157     blackbox.io.sys_rst       :=io.port.sys_rst
 158     //mig.device_temp         :- unconnceted
 159   }
 160 }