src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707mig
   3
   4 import Chisel._
   5 import chisel3.experimental.{Analog,attach}
   6 import freechips.rocketchip.amba.axi4._
   7 import freechips.rocketchip.config.Parameters
   8 import freechips.rocketchip.coreplex._
   9 import freechips.rocketchip.diplomacy._
  10 import freechips.rocketchip.tilelink._
  11 import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
  12
  13 trait HasXilinxVC707MIGParameters {
  14 }
  15
  16 class XilinxVC707MIGPads extends Bundle with VC707MIGIODDR
  17
  18 class XilinxVC707MIGIO extends Bundle with VC707MIGIODDR
  19                                       with VC707MIGIOClocksReset
  20
  21 class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
  22   val device = new MemoryDevice
  23   val node = TLInputNode()
  24   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
  25     slaves = Seq(AXI4SlaveParameters(
  26       address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
  27       resources     = device.reg,
  28       regionType    = RegionType.UNCACHED,
  29       executable    = true,
  30       supportsWrite = TransferSizes(1, 256*8),
  31       supportsRead  = TransferSizes(1, 256*8))),
  32     beatBytes = 8)))
  33
  34   val xing    = LazyModule(new TLAsyncCrossing)
  35   val toaxi4  = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
  36   val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
  37   val deint   = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
  38   val yank    = LazyModule(new AXI4UserYanker)
  39   val buffer  = LazyModule(new AXI4Buffer)
  40
  41   xing.node := node
  42   val monitor = (toaxi4.node := xing.node)
  43   axi4 := buffer.node
  44   buffer.node := yank.node
  45   yank.node := deint.node
  46   deint.node := indexer.node
  47   indexer.node := toaxi4.node
  48
  49   lazy val module = new LazyModuleImp(this) {
  50     val io = new Bundle {
  51       val port = new XilinxVC707MIGIO
  52       val tl = node.bundleIn
  53     }
  54
  55     //MIG black box instantiation
  56     val blackbox = Module(new vc707mig)
  57
  58     //pins to top level
  59
  60     //inouts
  61     attach(io.port.ddr3_dq,blackbox.io.ddr3_dq)
  62     attach(io.port.ddr3_dqs_n,blackbox.io.ddr3_dqs_n)
  63     attach(io.port.ddr3_dqs_p,blackbox.io.ddr3_dqs_p)
  64
  65     //outputs
  66     io.port.ddr3_addr         := blackbox.io.ddr3_addr
  67     io.port.ddr3_ba           := blackbox.io.ddr3_ba
  68     io.port.ddr3_ras_n        := blackbox.io.ddr3_ras_n
  69     io.port.ddr3_cas_n        := blackbox.io.ddr3_cas_n
  70     io.port.ddr3_we_n         := blackbox.io.ddr3_we_n
  71     io.port.ddr3_reset_n      := blackbox.io.ddr3_reset_n
  72     io.port.ddr3_ck_p         := blackbox.io.ddr3_ck_p
  73     io.port.ddr3_ck_n         := blackbox.io.ddr3_ck_n
  74     io.port.ddr3_cke          := blackbox.io.ddr3_cke
  75     io.port.ddr3_cs_n         := blackbox.io.ddr3_cs_n
  76     io.port.ddr3_dm           := blackbox.io.ddr3_dm
  77     io.port.ddr3_odt          := blackbox.io.ddr3_odt
  78
  79     //inputs
  80     //NO_BUFFER clock
  81     blackbox.io.sys_clk_i     := io.port.sys_clk_i
  82
  83     //user interface signals
  84     val axi_async = axi4.bundleIn(0)
  85     xing.module.io.in_clock := clock
  86     xing.module.io.in_reset := reset
  87     xing.module.io.out_clock := blackbox.io.ui_clk
  88     xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
  89     (Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm =>
  90       lm.module.clock := blackbox.io.ui_clk
  91       lm.module.reset := blackbox.io.ui_clk_sync_rst
  92     }
  93
  94     io.port.ui_clk            := blackbox.io.ui_clk
  95     io.port.ui_clk_sync_rst   := blackbox.io.ui_clk_sync_rst
  96     io.port.mmcm_locked       := blackbox.io.mmcm_locked
  97     blackbox.io.aresetn       := io.port.aresetn
  98     blackbox.io.app_sr_req    := Bool(false)
  99     blackbox.io.app_ref_req   := Bool(false)
 100     blackbox.io.app_zq_req    := Bool(false)
 101     //app_sr_active           := unconnected
 102     //app_ref_ack             := unconnected
 103     //app_zq_ack              := unconnected
 104
 105     //slave AXI interface write address ports
 106     blackbox.io.s_axi_awid    := axi_async.aw.bits.id
 107     blackbox.io.s_axi_awaddr  := axi_async.aw.bits.addr //truncation ??
 108     blackbox.io.s_axi_awlen   := axi_async.aw.bits.len
 109     blackbox.io.s_axi_awsize  := axi_async.aw.bits.size
 110     blackbox.io.s_axi_awburst := axi_async.aw.bits.burst
 111     blackbox.io.s_axi_awlock  := axi_async.aw.bits.lock
 112     blackbox.io.s_axi_awcache := UInt("b0011")
 113     blackbox.io.s_axi_awprot  := axi_async.aw.bits.prot
 114     blackbox.io.s_axi_awqos   := axi_async.aw.bits.qos
 115     blackbox.io.s_axi_awvalid := axi_async.aw.valid
 116     axi_async.aw.ready        := blackbox.io.s_axi_awready
 117
 118     //slave interface write data ports
 119     blackbox.io.s_axi_wdata   := axi_async.w.bits.data
 120     blackbox.io.s_axi_wstrb   := axi_async.w.bits.strb
 121     blackbox.io.s_axi_wlast   := axi_async.w.bits.last
 122     blackbox.io.s_axi_wvalid  := axi_async.w.valid
 123     axi_async.w.ready         := blackbox.io.s_axi_wready
 124
 125     //slave interface write response
 126     blackbox.io.s_axi_bready  := axi_async.b.ready
 127     axi_async.b.bits.id       := blackbox.io.s_axi_bid
 128     axi_async.b.bits.resp     := blackbox.io.s_axi_bresp
 129     axi_async.b.valid         := blackbox.io.s_axi_bvalid
 130
 131     //slave AXI interface read address ports
 132     blackbox.io.s_axi_arid    := axi_async.ar.bits.id
 133     blackbox.io.s_axi_araddr  := axi_async.ar.bits.addr //truncation ??
 134     blackbox.io.s_axi_arlen   := axi_async.ar.bits.len
 135     blackbox.io.s_axi_arsize  := axi_async.ar.bits.size
 136     blackbox.io.s_axi_arburst := axi_async.ar.bits.burst
 137     blackbox.io.s_axi_arlock  := axi_async.ar.bits.lock
 138     blackbox.io.s_axi_arcache := UInt("b0011")
 139     blackbox.io.s_axi_arprot  := axi_async.ar.bits.prot
 140     blackbox.io.s_axi_arqos   := axi_async.ar.bits.qos
 141     blackbox.io.s_axi_arvalid := axi_async.ar.valid
 142     axi_async.ar.ready        := blackbox.io.s_axi_arready
 143
 144     //slace AXI interface read data ports
 145     blackbox.io.s_axi_rready  := axi_async.r.ready
 146     axi_async.r.bits.id       := blackbox.io.s_axi_rid
 147     axi_async.r.bits.data     := blackbox.io.s_axi_rdata
 148     axi_async.r.bits.resp     := blackbox.io.s_axi_rresp
 149     axi_async.r.bits.last     := blackbox.io.s_axi_rlast
 150     axi_async.r.valid         := blackbox.io.s_axi_rvalid
 151
 152     //misc
 153     io.port.init_calib_complete := blackbox.io.init_calib_complete
 154     blackbox.io.sys_rst       :=io.port.sys_rst
 155     //mig.device_temp         :- unconnceted
 156   }
 157 }