src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707pciex1
   3
   4 import Chisel._
   5 import config._
   6 import diplomacy._
   7 import uncore.tilelink2._
   8 import uncore.axi4._
   9 import rocketchip._
  10 import sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
  11 import sifive.blocks.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
  12
  13 class XilinxVC707PCIeX1Pads extends Bundle with VC707AXIToPCIeX1IOSerial
  14
  15 class XilinxVC707PCIeX1IO extends Bundle with VC707AXIToPCIeX1IOSerial
  16                                          with VC707AXIToPCIeX1IOClocksReset {
  17   val axi_ctl_aresetn = Bool(INPUT)
  18   val REFCLK_rxp = Bool(INPUT)
  19   val REFCLK_rxn = Bool(INPUT)
  20 }
  21
  22 class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
  23   val slave = TLInputNode()
  24   val control = TLInputNode()
  25   val master = TLOutputNode()
  26   val intnode = IntSourceNode(1)
  27
  28   val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
  29   axi_to_pcie_x1.slave   := TLToAXI4(idBits=4)(slave)
  30   axi_to_pcie_x1.control := AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control))
  31   master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
  32
  33   lazy val module = new LazyModuleImp(this) {
  34     val io = new Bundle {
  35       val port = new XilinxVC707PCIeX1IO
  36       val slave_in = slave.bundleIn
  37       val control_in = control.bundleIn
  38       val master_out = master.bundleOut
  39       val interrupt = intnode.bundleOut
  40     }
  41
  42     io.port <> axi_to_pcie_x1.module.io.port
  43     io.interrupt(0)(0) := axi_to_pcie_x1.module.io.interrupt_out
  44
  45     //PCIe Reference Clock
  46     val ibufds_gte2 = Module(new IBUFDS_GTE2)
  47     axi_to_pcie_x1.module.io.REFCLK := ibufds_gte2.io.O
  48     ibufds_gte2.io.CEB := UInt(0)
  49     ibufds_gte2.io.I := io.port.REFCLK_rxp
  50     ibufds_gte2.io.IB := io.port.REFCLK_rxn
  51   }
  52 }