src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707pciex1
   3
   4 import Chisel._
   5 import freechips.rocketchip.coreplex.{HasInterruptBus, HasSystemBus}
   6 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
   7
   8 trait HasSystemXilinxVC707PCIeX1 extends HasSystemBus with HasInterruptBus {
   9   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
  10
  11   sbus.fromAsyncFIFOMaster() := xilinxvc707pcie.master
  12   xilinxvc707pcie.slave := sbus.toAsyncFixedWidthSlaves()
  13   xilinxvc707pcie.control := sbus.toAsyncFixedWidthSlaves()
  14   ibus.fromAsync := xilinxvc707pcie.intnode
  15 }
  16
  17 trait HasSystemXilinxVC707PCIeX1Bundle {
  18   val xilinxvc707pcie: XilinxVC707PCIeX1IO
  19   def connectXilinxVC707PCIeX1ToPads(pads: XilinxVC707PCIeX1Pads) {
  20     pads <> xilinxvc707pcie
  21   }
  22 }
  23
  24 trait HasSystemXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp
  25     with HasSystemXilinxVC707PCIeX1Bundle {
  26   val outer: HasSystemXilinxVC707PCIeX1
  27   val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO)
  28
  29   xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
  30
  31   outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
  32   outer.xilinxvc707pcie.module.reset := ~xilinxvc707pcie.axi_aresetn
  33 }