src/main/scala/ip/xilinx/vc707mig/vc707mig.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.ip.xilinx.vc707mig
   3
   4 import Chisel._
   5 import chisel3.experimental.{Analog,attach}
   6 import freechips.rocketchip.config._
   7
   8 // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0
   9 // Black Box
  10
  11 trait VC707MIGIODDR extends Bundle {
  12   val ddr3_addr             = Bits(OUTPUT,14)
  13   val ddr3_ba               = Bits(OUTPUT,3)
  14   val ddr3_ras_n            = Bool(OUTPUT)
  15   val ddr3_cas_n            = Bool(OUTPUT)
  16   val ddr3_we_n             = Bool(OUTPUT)
  17   val ddr3_reset_n          = Bool(OUTPUT)
  18   val ddr3_ck_p             = Bits(OUTPUT,1)
  19   val ddr3_ck_n             = Bits(OUTPUT,1)
  20   val ddr3_cke              = Bits(OUTPUT,1)
  21   val ddr3_cs_n             = Bits(OUTPUT,1)
  22   val ddr3_dm               = Bits(OUTPUT,8)
  23   val ddr3_odt              = Bits(OUTPUT,1)
  24
  25   val ddr3_dq               = Analog(64.W)
  26   val ddr3_dqs_n            = Analog(8.W)
  27   val ddr3_dqs_p            = Analog(8.W)
  28 }
  29
  30 //reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
  31 trait VC707MIGIOClocksReset extends Bundle {
  32   //inputs
  33   //"NO_BUFFER" clock source (must be connected to IBUF outside of IP)
  34   val sys_clk_i             = Bool(INPUT)
  35   //user interface signals
  36   val ui_clk                = Clock(OUTPUT)
  37   val ui_clk_sync_rst       = Bool(OUTPUT)
  38   val mmcm_locked           = Bool(OUTPUT)
  39   val aresetn               = Bool(INPUT)
  40   //misc
  41   val init_calib_complete   = Bool(OUTPUT)
  42   val sys_rst               = Bool(INPUT)
  43 }
  44
  45 //scalastyle:off
  46 //turn off linter: blackbox name must match verilog module
  47 class vc707mig(implicit val p:Parameters) extends BlackBox
  48 {
  49   val io = new Bundle with VC707MIGIODDR
  50                       with VC707MIGIOClocksReset {
  51     // User interface signals
  52     val app_sr_req            = Bool(INPUT)
  53     val app_ref_req           = Bool(INPUT)
  54     val app_zq_req            = Bool(INPUT)
  55     val app_sr_active         = Bool(OUTPUT)
  56     val app_ref_ack           = Bool(OUTPUT)
  57     val app_zq_ack            = Bool(OUTPUT)
  58     //axi_s
  59     //slave interface write address ports
  60     val s_axi_awid            = Bits(INPUT,4)
  61     val s_axi_awaddr          = Bits(INPUT,30)
  62     val s_axi_awlen           = Bits(INPUT,8)
  63     val s_axi_awsize          = Bits(INPUT,3)
  64     val s_axi_awburst         = Bits(INPUT,2)
  65     val s_axi_awlock          = Bits(INPUT,1)
  66     val s_axi_awcache         = Bits(INPUT,4)
  67     val s_axi_awprot          = Bits(INPUT,3)
  68     val s_axi_awqos           = Bits(INPUT,4)
  69     val s_axi_awvalid         = Bool(INPUT)
  70     val s_axi_awready         = Bool(OUTPUT)
  71     //slave interface write data ports
  72     val s_axi_wdata           = Bits(INPUT,64)
  73     val s_axi_wstrb           = Bits(INPUT,8)
  74     val s_axi_wlast           = Bool(INPUT)
  75     val s_axi_wvalid          = Bool(INPUT)
  76     val s_axi_wready          = Bool(OUTPUT)
  77     //slave interface write response ports
  78     val s_axi_bready          = Bool(INPUT)
  79     val s_axi_bid             = Bits(OUTPUT,4)
  80     val s_axi_bresp           = Bits(OUTPUT,2)
  81     val s_axi_bvalid          = Bool(OUTPUT)
  82     //slave interface read address ports
  83     val s_axi_arid            = Bits(INPUT,4)
  84     val s_axi_araddr          = Bits(INPUT,30)
  85     val s_axi_arlen           = Bits(INPUT,8)
  86     val s_axi_arsize          = Bits(INPUT,3)
  87     val s_axi_arburst         = Bits(INPUT,2)
  88     val s_axi_arlock          = Bits(INPUT,1)
  89     val s_axi_arcache         = Bits(INPUT,4)
  90     val s_axi_arprot          = Bits(INPUT,3)
  91     val s_axi_arqos           = Bits(INPUT,4)
  92     val s_axi_arvalid         = Bool(INPUT)
  93     val s_axi_arready         = Bool(OUTPUT)
  94     //slave interface read data ports
  95     val s_axi_rready          = Bool(INPUT)
  96     val s_axi_rid             = Bits(OUTPUT,4)
  97     val s_axi_rdata           = Bits(OUTPUT,64)
  98     val s_axi_rresp           = Bits(OUTPUT,2)
  99     val s_axi_rlast           = Bool(OUTPUT)
 100     val s_axi_rvalid          = Bool(OUTPUT)
 101     //misc
 102     val device_temp           = Bits(OUTPUT,12)
 103   }
 104 }
 105 //scalastyle:on