src/main/scala/util/RegMapFIFO.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.util
   3
   4 import Chisel._
   5 import regmapper._
   6
   7 // MSB indicates full status
   8 object NonBlockingEnqueue {
   9   def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
  10     val enqWidth = enq.bits.getWidth
  11     require(enqWidth > 0)
  12     require(regWidth > enqWidth)
  13     Seq(
  14       RegField(enqWidth,
  15         RegReadFn(UInt(0)),
  16         RegWriteFn((valid, data) => {
  17           enq.valid := valid
  18           enq.bits := data
  19           Bool(true)
  20         })),
  21       RegField(regWidth - enqWidth - 1),
  22       RegField.r(1, !enq.ready))
  23   }
  24 }
  25
  26 // MSB indicates empty status
  27 object NonBlockingDequeue {
  28   def apply(deq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
  29     val deqWidth = deq.bits.getWidth
  30     require(deqWidth > 0)
  31     require(regWidth > deqWidth)
  32     Seq(
  33       RegField.r(deqWidth,
  34         RegReadFn(ready => {
  35           deq.ready := ready
  36           (Bool(true), deq.bits)
  37         })),
  38       RegField(regWidth - deqWidth - 1),
  39       RegField.r(1, !deq.valid))
  40   }
  41 }