src/main/scala/util/ShiftReg.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.util
   3
   4 import Chisel._
   5
   6 object ShiftRegisterInit {
   7   def apply[T <: Data](in: T, n: Int, init: T): T =
   8     (0 until n).foldLeft(in) {
   9       case (next, _) => Reg(next, next = next, init = init)
  10     }
  11 }
  12
  13 object ShiftRegister
  14 {
  15   /** Returns the n-cycle delayed version of the input signal.
  16     *
  17     * @param in input to delay
  18     * @param n number of cycles to delay
  19     * @param en enable the shift
  20     * @param name set the elaborated name of the registers.
  21     */
  22   def apply[T <: Chisel.Data](in: T, n: Int, en: Chisel.Bool = Chisel.Bool(true), name: Option[String] = None): T = {
  23     // The order of tests reflects the expected use cases.
  24     if (n != 0) {
  25       val r = Chisel.RegEnable(apply(in, n-1, en, name), en)
  26       if (name.isDefined) r.suggestName(s"${name.get}_sync_${n-1}")
  27       r
  28     } else {
  29       in
  30     }
  31   }
  32
  33   /** Returns the n-cycle delayed version of the input signal with reset initialization.
  34     *
  35     * @param in input to delay
  36     * @param n number of cycles to delay
  37     * @param resetData reset value for each register in the shift
  38     * @param en enable the shift
  39     * @param name set the elaborated name of the registers.
  40     */
  41   def apply[T <: Chisel.Data](in: T, n: Int, resetData: T, en: Chisel.Bool, name: Option[String]): T = {
  42     // The order of tests reflects the expected use cases.
  43     if (n != 0) {
  44       val r = Chisel.RegEnable(apply(in, n-1, resetData, en, name), resetData, en)
  45       if (name.isDefined) r.suggestName(s"${name.get}_sync_${n-1}")
  46       r
  47     } else {
  48       in
  49     }
  50   }
  51 }