src/main/scala/util/ShiftRegister.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.util
   3
   4 import Chisel._
   5
   6 object ShiftRegisterInit {
   7   def apply[T <: Data](in: T, n: Int, init: T): T =
   8     (0 until n).foldLeft(in) {
   9       case (next, _) => Reg(next, next = next, init = init)
  10     }
  11 }
  12
  13
  14 // Similar to the Chisel ShiftRegister but allows the user to suggest a
  15 // name to the registers within the module that get instantiated
  16 object ShiftRegister
  17 {
  18   /** Returns the n-cycle delayed version of the input signal.
  19     *
  20     * @param in input to delay
  21     * @param n number of cycles to delay
  22     * @param en enable the shift
  23     * @param name set the elaborated name of the registers.
  24     */
  25   def apply[T <: Chisel.Data](in: T, n: Int, en: Chisel.Bool = Chisel.Bool(true), name: Option[String] = None): T = {
  26     // The order of tests reflects the expected use cases.
  27     if (n != 0) {
  28       val r = Chisel.RegEnable(apply(in, n-1, en, name), en)
  29       if (name.isDefined) r.suggestName(s"${name.get}_sync_${n-1}")
  30       r
  31     } else {
  32       in
  33     }
  34   }
  35
  36   /** Returns the n-cycle delayed version of the input signal with reset initialization.
  37     *
  38     * @param in input to delay
  39     * @param n number of cycles to delay
  40     * @param resetData reset value for each register in the shift
  41     * @param en enable the shift
  42     * @param name set the elaborated name of the registers.
  43     */
  44   def apply[T <: Chisel.Data](in: T, n: Int, resetData: T, en: Chisel.Bool, name: Option[String]): T = {
  45     // The order of tests reflects the expected use cases.
  46     if (n != 0) {
  47       val r = Chisel.RegEnable(apply(in, n-1, resetData, en, name), resetData, en)
  48       if (name.isDefined) r.suggestName(s"${name.get}_sync_${n-1}")
  49       r
  50     } else {
  51       in
  52     }
  53   }
  54 }