sifive-blocks: trust diplomacy to get names right

[sifive-blocks.git] / src / main / scala / devices / pwm / PWMPeriphery.scala

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index 992699fa6c907e949a3e168eb7913787ed02b0bd..86e9ad2f3f8756aca2db7300190f28131faf0497 100644 (file)
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -30,8 +30,8 @@ class PWMGPIOPort(c: PWMBundleConfig)(implicit p: Parameters) extends Module {
 trait PeripheryPWM {
   this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
 
-  val pwmDevices = (pwmConfigs.zipWithIndex) map { case (c, i) =>
-    val pwm = LazyModule(new TLPWM(c) { override lazy val  valName = Some(s"pwm$i") })
+  val pwm = (pwmConfigs.zipWithIndex) map { case (c, i) =>
+    val pwm = LazyModule(new TLPWM(c))
     pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := pwm.intnode
     pwm
@@ -52,7 +52,7 @@ trait PeripheryPWMModule {
     val outer: PeripheryPWM
     val io: PeripheryPWMBundle
   } =>
-  (io.pwms.zipWithIndex zip outer.pwmDevices) foreach { case ((io, i), device) =>
+  (io.pwms.zipWithIndex zip outer.pwm) foreach { case ((io, i), device) =>
     io.port := device.module.io.gpio
   }
 }