shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate

[sifive-blocks.git] / src / main / scala / devices / uart / UARTPeriphery.scala

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index 00e5fdd856e5003fda3062050b8fe172a07d85f0..f29716c8a350f80fe1b23b11b9ef5b76557c46fa 100644 (file)
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -4,10 +4,10 @@ package sifive.blocks.devices.uart
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.config.Field
+import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
 import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 import sifive.blocks.devices.pinctrl.{Pin}
-import sifive.blocks.util.ShiftRegisterInit
 
 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
 
@@ -51,7 +51,7 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
     withClockAndReset(clock, reset) {
       txd.outputPin(uart.txd)
       val rxd_t = rxd.inputPin()
-      uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
+      uart.rxd := SyncResetSynchronizerShiftReg(rxd_t, syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
     }
   }
 }