xilinx pcie: bytes, not bits

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707pciex1 / XilinxVC707PCIeX1.scala

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
index a795bf0cba72314ffb71fece79f01cea9d223998..bd3b1ef9fd8c818a87b940cda88e0cd3c67274c7 100644 (file)
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
@@ -28,7 +28,7 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
   val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
   axi_to_pcie_x1.slave   := TLToAXI4(idBits=4)(slave)
   axi_to_pcie_x1.control := AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control))
-  master := TLWidthWidget(64)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
+  master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
 
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {