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(parent: ca7555b) | patch
xilinx pcie: bytes, not bits
authorWesley W. Terpstra <wesley@sifive.com>
Wed, 7 Dec 2016 00:13:12 +0000 (16:13 -0800)
committerWesley W. Terpstra <wesley@sifive.com>
Wed, 7 Dec 2016 00:13:12 +0000 (16:13 -0800)
commit1443834186bad8981ed29801d3703c05218ce6dc
tree7b2920c838f2855feb68385132140cee974c9574tree
parentca7555bd4d868c39cd2d92395c985e57dd3a197acommit | diff
xilinx pcie: bytes, not bits

This bug amazingly compiled correctly and ran correctly!

It was saved by the AXIFragmenter which turned the "narrow burst" into
individual beats that then got converted to 64b in TileLink land via
inspection of the mask bits.

The consequence is that AXI bus mastering proceeded at one word per
DDR round-trip. Now it is one cache line per DDR round-trip. When we
get L2 back in the design, it should really fly!
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala diff | blob | history
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