rename l2FrontendBus as fsb

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707pciex1 / XilinxVC707PCIeX1Periphery.scala

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
index f37f7f9da272b571bcbfe2bdb4e89fb951d39200..d64d19aff9546e81dfb0f24861ec945dd0024c30 100644 (file)
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
@@ -13,7 +13,7 @@ import uncore.tilelink2.TLWidthWidget
 trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
 
   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
-  l2FrontendBus.node := xilinxvc707pcie.master
+  fsb.node := xilinxvc707pcie.master
   xilinxvc707pcie.slave   := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
   xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
   intBus.intnode := xilinxvc707pcie.intnode