axi4: switch to new pipelined converters

[sifive-blocks.git] / src / main / scala / ip / xilinx / vc707axi_to_pcie_x1 / vc707axi_to_pcie_x1.scala

diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
index 2e826db582b0005ac608c11b4d4339e29e554e32..d9ffe8b9e7cd42f5d159095410ee92fd673b9047 100644 (file)
--- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
+++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
@@ -182,7 +182,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
         "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt),
         "interrupt-map"      -> Seq(1, 2, 3, 4).flatMap(ofMap),
         "ranges"             -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _)) =>
-                                                               ResourceMapping(address, 0) },
+                                                               ResourceMapping(address, BigInt(0x02000000) << 64) },
         "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map(
           "interrupt-controller" -> Nil,
           "#address-cells"       -> ofInt(0),
@@ -197,8 +197,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
       resources     = Seq(Resource(device, "ranges")),
       executable    = true,
       supportsWrite = TransferSizes(1, 256),
-      supportsRead  = TransferSizes(1, 256),
-      interleavedId = Some(0))), // the Xilinx IP is friendly
+      supportsRead  = TransferSizes(1, 256))),
     beatBytes = 8)))
 
   val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
@@ -206,8 +205,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
       address       = List(AddressSet(0x50000000L, 0x03ffffffL)),
       resources     = device.reg,
       supportsWrite = TransferSizes(1, 4),
-      supportsRead  = TransferSizes(1, 4),
-      interleavedId = Some(0))), // no read interleaving b/c AXI-lite
+      supportsRead  = TransferSizes(1, 4))),
     beatBytes = 4)))
 
   val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(