resources = Seq(Resource(device, "ranges")),
executable = true,
supportsWrite = TransferSizes(1, 256),
- supportsRead = TransferSizes(1, 256),
- interleavedId = Some(0))), // the Xilinx IP is friendly
+ supportsRead = TransferSizes(1, 256))),
beatBytes = 8)))
val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
address = List(AddressSet(0x50000000L, 0x03ffffffL)),
resources = device.reg,
supportsWrite = TransferSizes(1, 4),
- supportsRead = TransferSizes(1, 4),
- interleavedId = Some(0))), // no read interleaving b/c AXI-lite
+ supportsRead = TransferSizes(1, 4))),
beatBytes = 4)))
val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(