xilinx pcie: put buffers before the outputs to the controller
authorWesley W. Terpstra <wesley@sifive.com>
Sat, 21 Jan 2017 06:38:27 +0000 (22:38 -0800)
committerWesley W. Terpstra <wesley@sifive.com>
Sat, 21 Jan 2017 06:38:27 +0000 (22:38 -0800)
commitd61d86e08417ae182e7f2e8aabebc193941ce31a
tree51de22ed8886ad99bf34226550a1c483e5335254
parentc68e44ec554e47ca07e8f3e42246436779a9764f
xilinx pcie: put buffers before the outputs to the controller
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala