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Made regs 32-bit word aligned to match the rest of the system
author
Alex Solomatnikov
<sols@sifive.com>
Thu, 9 Feb 2017 19:36:19 +0000
(11:36 -0800)
committer
Alex Solomatnikov
<sols@sifive.com>
Thu, 9 Feb 2017 19:36:19 +0000
(11:36 -0800)
src/main/scala/devices/i2c/I2CCtrlRegs.scala
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diff --git
a/src/main/scala/devices/i2c/I2CCtrlRegs.scala
b/src/main/scala/devices/i2c/I2CCtrlRegs.scala
index 1a69783a39d0a6b4057735b028962eeda61ea619..aaa619795b9fae5ed25f282821d594c4a4724315 100644
(file)
--- a/
src/main/scala/devices/i2c/I2CCtrlRegs.scala
+++ b/
src/main/scala/devices/i2c/I2CCtrlRegs.scala
@@
-6,8
+6,8
@@
package sifive.blocks.devices.i2c
object I2CCtrlRegs {
val prescaler_lo = 0x00 // low byte clock prescaler register
object I2CCtrlRegs {
val prescaler_lo = 0x00 // low byte clock prescaler register
- val prescaler_hi = 0x0
1
// high byte clock prescaler register
- val control = 0x0
2
// control register
- val data = 0x0
3
// write: transmit byte, read: receive byte
- val cmd_status = 0x
04
// write: command, read: status
+ val prescaler_hi = 0x0
4
// high byte clock prescaler register
+ val control = 0x0
8
// control register
+ val data = 0x0
c
// write: transmit byte, read: receive byte
+ val cmd_status = 0x
10
// write: command, read: status
}
}