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update TLRegisterNode to take Seq of AddressSet
author
Yunsup Lee
<yunsup@sifive.com>
Wed, 22 Mar 2017 05:12:37 +0000
(22:12 -0700)
committer
Yunsup Lee
<yunsup@sifive.com>
Wed, 22 Mar 2017 05:12:37 +0000
(22:12 -0700)
src/main/scala/devices/spi/TLSPI.scala
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diff --git
a/src/main/scala/devices/spi/TLSPI.scala
b/src/main/scala/devices/spi/TLSPI.scala
index b20b5246c3e5a813ee51e67f16d0712a56c6bede..5c5b9bfe5409fd91a1bd411e16d5cbc420a14283 100644
(file)
--- a/
src/main/scala/devices/spi/TLSPI.scala
+++ b/
src/main/scala/devices/spi/TLSPI.scala
@@
-110,7
+110,7
@@
class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS
abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
require(isPow2(c.rSize))
val device = new SimpleDevice("spi", Seq("sifive,spi0"))
abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
require(isPow2(c.rSize))
val device = new SimpleDevice("spi", Seq("sifive,spi0"))
- val rnode = TLRegisterNode(address =
AddressSet(c.rAddress, c.rSize-1
), device = device, beatBytes = w)
+ val rnode = TLRegisterNode(address =
Seq(AddressSet(c.rAddress, c.rSize-1)
), device = device, beatBytes = w)
val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
}
val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
}