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RegMapFIFO: amoor.w can do thread-safe TX
author
Wesley W. Terpstra
<wesley@sifive.com>
Sat, 3 Dec 2016 01:48:17 +0000
(17:48 -0800)
committer
Wesley W. Terpstra
<wesley@sifive.com>
Sat, 3 Dec 2016 01:48:17 +0000
(17:48 -0800)
src/main/scala/util/RegMapFIFO.scala
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diff --git
a/src/main/scala/util/RegMapFIFO.scala
b/src/main/scala/util/RegMapFIFO.scala
index aaeba59bff55ff651459f42b02c58ba59ce6c140..3e4548242d1b63a0ebde1016d00d68c554a67925 100644
(file)
--- a/
src/main/scala/util/RegMapFIFO.scala
+++ b/
src/main/scala/util/RegMapFIFO.scala
@@
-8,18
+8,24
@@
import regmapper._
object NonBlockingEnqueue {
def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
val enqWidth = enq.bits.getWidth
object NonBlockingEnqueue {
def apply(enq: DecoupledIO[UInt], regWidth: Int = 32): Seq[RegField] = {
val enqWidth = enq.bits.getWidth
+ val quash = Wire(Bool())
require(enqWidth > 0)
require(regWidth > enqWidth)
Seq(
RegField(enqWidth,
RegReadFn(UInt(0)),
RegWriteFn((valid, data) => {
require(enqWidth > 0)
require(regWidth > enqWidth)
Seq(
RegField(enqWidth,
RegReadFn(UInt(0)),
RegWriteFn((valid, data) => {
- enq.valid := valid
+ enq.valid := valid
&& !quash
enq.bits := data
Bool(true)
})),
RegField(regWidth - enqWidth - 1),
enq.bits := data
Bool(true)
})),
RegField(regWidth - enqWidth - 1),
- RegField.r(1, !enq.ready))
+ RegField(1,
+ !enq.ready,
+ RegWriteFn((valid, data) => {
+ quash := valid && data(0)
+ Bool(true)
+ })))
}
}
}
}