- val load = Reg(init = Bool(false)) // load shift register
- val shift = Reg(init = Bool(false)) // shift shift register
- val cmdAck = Reg(init = Bool(false)) // also done
- val receivedAck = Reg(init = Bool(false)) // from I2C slave
- val go = (cmd.read | cmd.write | cmd.stop) & ~cmdAck // CHECK: why stop instead of start?
+ val load = Reg(init = false.B) // load shift register
+ val shift = Reg(init = false.B) // shift shift register
+ val cmdAck = Reg(init = false.B) // also done
+ val receivedAck = Reg(init = false.B) // from I2C slave
+ val go = (cmd.read | cmd.write | cmd.stop) & !cmdAck