try chip_r adder test (works)

diff --git a/ls180/post_pnr/cocotb/Makefile b/ls180/post_pnr/cocotb/Makefile
index cb4cc70b30138743f9f6dc074932158cfbf94daf..ea51d19905832589d7f8891e59b41673d3dddc1b 100644 (file)
--- a/ls180/post_pnr/cocotb/Makefile
+++ b/ls180/post_pnr/cocotb/Makefile
@@ -18,7 +18,7 @@ VHDL_SOURCES = \
   $(wildcard $(VSTDIR)/*.vst) \
   $(wildcard $(NSXLIBDIR)/*.vhd) \
   $(wildcard $(NIOLIBDIR)/*.vhd)
-TOPLEVEL=chip
+TOPLEVEL=chip_r
 TOPLEVEL_LANG=vhdl
 MODULE=test
 SIM=ghdl

diff --git a/ls180/post_pnr/cocotb/test.py b/ls180/post_pnr/cocotb/test.py
index 4d79d0b2047a9061edd3f3f12c7385c00b4fbaa9..9bf57fdcb94e3a3e836b0f2b45c2cc9dfda2cc78 100644 (file)
--- a/ls180/post_pnr/cocotb/test.py
+++ b/ls180/post_pnr/cocotb/test.py
@@ -38,7 +38,7 @@ def setup_sim(dut, *, clk_period, run):
     dut.iovss <= 0
     dut.sys_rst <= 1
     dut.sys_clk <= 0
-    # adder test (ignore)
+    # adder test (ignore this)
     #dut.a <= 3
     #dut.b <= 2