+++ /dev/null
-niolib/
-nsxlib/
-obj/
-vst_src/
-__pycache__/
-.*.sw?
+++ /dev/null
-.PHONY: all corona prepare cocotb gitupdate
-
-all: prepare cocotb
-
-# submodule update
-gitupdate:
- git submodule update --init --remote
-
-# gets the nsxlib and niolib files, and munges the contents of vst_src
-prepare:
- ./vbe2vst.py
- ./vst_correct.py
-
-# runs cocotb test
-cocotb:
- (cd cocotb && ./run_ghdl.sh)
-
-# builds just for fun (double-check) ghdl works
-corona:
- ./vhd2obj.py
- (cd obj && ghdl -e -g --std=08 corona)
- (cd obj && ghdl -r -g --std=08 corona)
-
+++ /dev/null
-# Dependencies
-
-* make gitupdate
-* https://git.libre-soc.org/?p=dev-env-setup.git;a=summary
- - run coriolis2_chroot (to set up coriolis2)
- - run install-hdl-apt-reqs
-* install ghdl (working: GHDL 1.0-dev (v0.37.0-819-g9828b513) [Dunoon edition])
- this is very likely to have to be done from source
-* install cocotb (can be done from source https://github.com/cocotb/cocotb)
-
-# Build
-
-* make one experiment with a JTAG tap (experiments10 or experiments9)
-* copy *.vst into vst_src except cts files, chip.vst and chip_r.vst
-* make cocotb
+++ /dev/null
-CURDIR=$(realpath .)
-TOPDIR=$(realpath ..)
-
-ifeq ($(PYTHONPATH),)
- PYTHONPATH := $(TOPDIR)
-else
- PYTHONPATH := $(TOPDIR):$(PYTHONPATH)
-endif
-export PYTHONPATH
-
-VSTDIR=$(TOPDIR)/vst_src
-NSXLIBDIR=$(TOPDIR)/nsxlib
-NIOLIBDIR=$(TOPDIR)/niolib
-VHDL_SOURCES = \
- $(wildcard $(VSTDIR)/*.vst) \
- $(wildcard $(NSXLIBDIR)/*.vhd) \
- $(wildcard $(NIOLIBDIR)/*.vhd)
-TOPLEVEL=corona
-TOPLEVEL_LANG=vhdl
-MODULE=test
-SIM=ghdl
-GPI_IMPL=vhpi
-GHDL_ARGS=--std=08
-SIM_ARGS=--wave=test.ghw
-
-COCOTBMAKEFILESDIR=$(shell cocotb-config --makefiles)
-
-include $(COCOTBMAKEFILESDIR)/Makefile.sim
+++ /dev/null
-#!/bin/sh
-rm -fr results_*.xml sim_build_*
-
+++ /dev/null
-!Loading device with 'idcode' instruction.
-SIR 4 TDI (1);
-SDR 32 TDI (00000000) TDO (000018FF) ;
-
+++ /dev/null
-#!/bin/sh
-
-# Only run test in reset state as running CPU takes too much time to simulate
-make \
- SIM=ghdl \
- COCOTB_RESULTS_FILE=results_iverilog.xml \
- COCOTB_HDL_TIMEUNIT=100ps \
- TESTCASE="idcode_reset,idcodesvf_reset" \
- SIM_BUILD=sim_build_iverilog
-
-
+++ /dev/null
-import cocotb
-from cocotb.clock import Clock
-from cocotb.triggers import Timer
-from cocotb.utils import get_sim_steps
-from cocotb.binary import BinaryValue
-
-from c4m.cocotb.jtag.c4m_jtag import JTAG_Master
-from c4m.cocotb.jtag.c4m_jtag_svfcocotb import SVF_Executor
-
-#
-# Helper functions
-#
-
-def setup_sim(dut, *, clk_period, run):
- """Initialize CPU and setup clock"""
-
- clk_steps = get_sim_steps(clk_period, "ns")
- cocotb.fork(Clock(dut.clk_from_pad, clk_steps).start())
-
- dut.rst_from_pad <= 1
- dut.clk_from_pad <= 0
- if run:
- yield Timer(int(10.5*clk_steps))
- dut.rst_from_pad <= 0
- yield Timer(int(5*clk_steps))
-
-def setup_jtag(dut, *, tck_period):
- # Make this a generator
- if False:
- yield Timer(0)
- return JTAG_Master(dut.tck_from_pad, dut.tms_from_pad,
- dut.tdi_from_pad, dut.tdo_to_pad,
- clk_period=tck_period,
- ir_width=4)
-
-def execute_svf(dut, *, jtag, svf_filename):
- jtag_svf = SVF_Executor(jtag)
- with open(svf_filename, "r") as f:
- svf_deck = f.read()
- yield jtag_svf.run(svf_deck, p=dut._log.info)
-
-#
-# IDCODE using JTAG_master
-#
-
-def idcode(dut, *, jtag):
- #jtag.IDCODE = [0, 0, 0, 1]
- yield jtag.idcode()
- result1 = jtag.result
- dut._log.info("IDCODE1: {}".format(result1))
- assert(result1 == BinaryValue("00000000000000000001100011111111"))
-
- yield jtag.idcode()
- result2 = jtag.result
- dut._log.info("IDCODE2: {}".format(result2))
-
- assert(result1 == result2)
-
-@cocotb.test()
-def idcode_reset(dut):
- dut._log.info("Running IDCODE test; cpu in reset...")
-
- clk_period = 100 # 10MHz
- tck_period = 300 # 3MHz
-
- yield from setup_sim(dut, clk_period=clk_period, run=False)
- jtag = yield from setup_jtag(dut, tck_period = tck_period)
-
- yield from idcode(dut, jtag=jtag)
-
- dut._log.info("IDCODE test completed")
-
-@cocotb.test()
-def idcode_run(dut):
- dut._log.info("Running IDCODE test; cpu running...")
-
- clk_period = 100 # 10MHz
- tck_period = 300 # 3MHz
-
- yield from setup_sim(dut, clk_period=clk_period, run=True)
- jtag = yield from setup_jtag(dut, tck_period = tck_period)
-
- yield from idcode(dut, jtag=jtag)
-
- dut._log.info("IDCODE test completed")
-
-#
-# Read IDCODE from SVF file
-#
-
-@cocotb.test()
-def idcodesvf_reset(dut):
- dut._log.info("Running IDCODE through SVF test; cpu in reset...")
-
- clk_period = 100 # 10MHz
- tck_period = 300 # 3MHz
-
- yield from setup_sim(dut, clk_period=clk_period, run=False)
- jtag = yield from setup_jtag(dut, tck_period = tck_period)
-
- yield from execute_svf(dut, jtag=jtag, svf_filename="idcode.svf")
-
- dut._log.info("IDCODE test completed")
-
-@cocotb.test()
-def idcode_run(dut):
- dut._log.info("Running IDCODE through test; cpu running...")
-
- clk_period = 100 # 10MHz
- tck_period = 300 # 3MHz
-
- yield from setup_sim(dut, clk_period=clk_period, run=True)
- jtag = yield from setup_jtag(dut, tck_period = tck_period)
-
- yield from execute_svf(dut, jtag=jtag, svf_filename="idcode.svf")
-
- dut._log.info("IDCODE test completed")
-
--- /dev/null
+niolib/
+nsxlib/
+obj/
+vst_src/
+__pycache__/
+.*.sw?
--- /dev/null
+.PHONY: all corona prepare cocotb gitupdate
+
+all: prepare cocotb
+
+# submodule update
+gitupdate:
+ git submodule update --init --remote
+
+# gets the nsxlib and niolib files, and munges the contents of vst_src
+prepare:
+ ./vbe2vst.py
+ ./vst_correct.py
+
+# runs cocotb test
+cocotb:
+ (cd cocotb && ./run_ghdl.sh)
+
+# builds just for fun (double-check) ghdl works
+corona:
+ ./vhd2obj.py
+ (cd obj && ghdl -e -g --std=08 corona)
+ (cd obj && ghdl -r -g --std=08 corona)
+
--- /dev/null
+# Dependencies
+
+* make gitupdate
+* https://git.libre-soc.org/?p=dev-env-setup.git;a=summary
+ - run coriolis2_chroot (to set up coriolis2)
+ - run install-hdl-apt-reqs
+* install ghdl (working: GHDL 1.0-dev (v0.37.0-819-g9828b513) [Dunoon edition])
+ this is very likely to have to be done from source
+* install cocotb (can be done from source https://github.com/cocotb/cocotb)
+
+# Build
+
+* make one experiment with a JTAG tap (experiments10 or experiments9)
+* copy *.vst into vst_src except cts files, chip.vst and chip_r.vst
+* make cocotb
--- /dev/null
+CURDIR=$(realpath .)
+TOPDIR=$(realpath ..)
+
+ifeq ($(PYTHONPATH),)
+ PYTHONPATH := $(TOPDIR)
+else
+ PYTHONPATH := $(TOPDIR):$(PYTHONPATH)
+endif
+export PYTHONPATH
+
+VSTDIR=$(TOPDIR)/vst_src
+NSXLIBDIR=$(TOPDIR)/nsxlib
+NIOLIBDIR=$(TOPDIR)/niolib
+VHDL_SOURCES = \
+ $(wildcard $(VSTDIR)/*.vst) \
+ $(wildcard $(NSXLIBDIR)/*.vhd) \
+ $(wildcard $(NIOLIBDIR)/*.vhd)
+TOPLEVEL=corona
+TOPLEVEL_LANG=vhdl
+MODULE=test
+SIM=ghdl
+GPI_IMPL=vhpi
+GHDL_ARGS=--std=08
+SIM_ARGS=--wave=test.ghw
+
+COCOTBMAKEFILESDIR=$(shell cocotb-config --makefiles)
+
+include $(COCOTBMAKEFILESDIR)/Makefile.sim
--- /dev/null
+#!/bin/sh
+rm -fr results_*.xml sim_build_*
+
--- /dev/null
+!Loading device with 'idcode' instruction.
+SIR 4 TDI (1);
+SDR 32 TDI (00000000) TDO (000018FF) ;
+
--- /dev/null
+#!/bin/sh
+
+# Only run test in reset state as running CPU takes too much time to simulate
+make \
+ SIM=ghdl \
+ COCOTB_RESULTS_FILE=results_iverilog.xml \
+ COCOTB_HDL_TIMEUNIT=100ps \
+ TESTCASE="idcode_reset,idcodesvf_reset" \
+ SIM_BUILD=sim_build_iverilog
+
+
--- /dev/null
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import Timer
+from cocotb.utils import get_sim_steps
+from cocotb.binary import BinaryValue
+
+from c4m.cocotb.jtag.c4m_jtag import JTAG_Master
+from c4m.cocotb.jtag.c4m_jtag_svfcocotb import SVF_Executor
+
+#
+# Helper functions
+#
+
+def setup_sim(dut, *, clk_period, run):
+ """Initialize CPU and setup clock"""
+
+ clk_steps = get_sim_steps(clk_period, "ns")
+ cocotb.fork(Clock(dut.clk_from_pad, clk_steps).start())
+
+ dut.rst_from_pad <= 1
+ dut.clk_from_pad <= 0
+ if run:
+ yield Timer(int(10.5*clk_steps))
+ dut.rst_from_pad <= 0
+ yield Timer(int(5*clk_steps))
+
+def setup_jtag(dut, *, tck_period):
+ # Make this a generator
+ if False:
+ yield Timer(0)
+ return JTAG_Master(dut.tck_from_pad, dut.tms_from_pad,
+ dut.tdi_from_pad, dut.tdo_to_pad,
+ clk_period=tck_period,
+ ir_width=4)
+
+def execute_svf(dut, *, jtag, svf_filename):
+ jtag_svf = SVF_Executor(jtag)
+ with open(svf_filename, "r") as f:
+ svf_deck = f.read()
+ yield jtag_svf.run(svf_deck, p=dut._log.info)
+
+#
+# IDCODE using JTAG_master
+#
+
+def idcode(dut, *, jtag):
+ #jtag.IDCODE = [0, 0, 0, 1]
+ yield jtag.idcode()
+ result1 = jtag.result
+ dut._log.info("IDCODE1: {}".format(result1))
+ assert(result1 == BinaryValue("00000000000000000001100011111111"))
+
+ yield jtag.idcode()
+ result2 = jtag.result
+ dut._log.info("IDCODE2: {}".format(result2))
+
+ assert(result1 == result2)
+
+@cocotb.test()
+def idcode_reset(dut):
+ dut._log.info("Running IDCODE test; cpu in reset...")
+
+ clk_period = 100 # 10MHz
+ tck_period = 300 # 3MHz
+
+ yield from setup_sim(dut, clk_period=clk_period, run=False)
+ jtag = yield from setup_jtag(dut, tck_period = tck_period)
+
+ yield from idcode(dut, jtag=jtag)
+
+ dut._log.info("IDCODE test completed")
+
+@cocotb.test()
+def idcode_run(dut):
+ dut._log.info("Running IDCODE test; cpu running...")
+
+ clk_period = 100 # 10MHz
+ tck_period = 300 # 3MHz
+
+ yield from setup_sim(dut, clk_period=clk_period, run=True)
+ jtag = yield from setup_jtag(dut, tck_period = tck_period)
+
+ yield from idcode(dut, jtag=jtag)
+
+ dut._log.info("IDCODE test completed")
+
+#
+# Read IDCODE from SVF file
+#
+
+@cocotb.test()
+def idcodesvf_reset(dut):
+ dut._log.info("Running IDCODE through SVF test; cpu in reset...")
+
+ clk_period = 100 # 10MHz
+ tck_period = 300 # 3MHz
+
+ yield from setup_sim(dut, clk_period=clk_period, run=False)
+ jtag = yield from setup_jtag(dut, tck_period = tck_period)
+
+ yield from execute_svf(dut, jtag=jtag, svf_filename="idcode.svf")
+
+ dut._log.info("IDCODE test completed")
+
+@cocotb.test()
+def idcode_run(dut):
+ dut._log.info("Running IDCODE through test; cpu running...")
+
+ clk_period = 100 # 10MHz
+ tck_period = 300 # 3MHz
+
+ yield from setup_sim(dut, clk_period=clk_period, run=True)
+ jtag = yield from setup_jtag(dut, tck_period = tck_period)
+
+ yield from execute_svf(dut, jtag=jtag, svf_filename="idcode.svf")
+
+ dut._log.info("IDCODE test completed")
+
--- /dev/null
+#!/usr/bin/env python3
+"""converts NIOLIB and NSXLIB from VBE into VHDL
+"""
+
+import os
+import sys
+
+# use the chroot to set up
+# https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=coriolis2-chroot;hb=HEAD
+# reason for using the chroot: it's standardised across the ls180 project
+
+VASY_CMD = "schroot -c coriolis -d /tmp -- ~/alliance/install/bin/vasy"
+ALLIANCEBASE = "../../alliance-check-toolkit/cells"
+ALLIANCE_LIBS = ['nsxlib', 'niolib']
+
+for libname in ALLIANCE_LIBS:
+
+ NSXLIB = "%s/%s" % (ALLIANCEBASE, libname)
+
+ os.system("mkdir -p %s" % libname)
+
+ for fname in os.listdir(NSXLIB):
+ if not fname.endswith(".vbe"):
+ continue
+ print (fname)
+ prefix = fname[:-4] # strip ".vbe"
+ os.system("cp %s/%s /tmp" % (NSXLIB, fname))
+ os.system("rm -f /tmp/%s.vhd" % (prefix))
+ os.system("%s -s -I vbe %s %s" % (VASY_CMD, fname, prefix))
+ os.system("cp /tmp/%s.vhd %s" % (prefix, libname))
--- /dev/null
+#!/usr/bin/env python3
+
+"""builds nsxlib and other VHD files into object files using ghdl
+"""
+
+import os
+import sys
+
+SRC = [('nsxlib', 'vhd'),
+ ('niolib', 'vhd'),
+ ('vst_src', 'vst')]
+
+# make and change to obj dir
+os.system("mkdir -p obj")
+cwd = os.getcwd()
+os.chdir("obj")
+
+for srcdir, suffix in SRC:
+ # run ghdl -a on every vhd / vst file
+ for fname in os.listdir("../%s" % srcdir):
+ if not fname.endswith(".%s" % suffix):
+ continue
+ print (fname)
+ prefix = fname[:-4] # strip ".vhd"
+ os.system("ghdl -a -g --std=08 ../%s/%s" % (srcdir, fname))
+
+# back to original dir
+os.chdir(cwd)
--- /dev/null
+#!/usr/bin/env python3
+
+"""makes corrections to vst source from coriolis2 P&R
+"""
+
+import os
+import sys
+
+# run through all files
+for fname in os.listdir("vst_src"):
+ if not fname.endswith(".vst"):
+ continue
+ print (fname)
+ # read the file
+ fname = "vst_src/"+fname
+ with open(fname) as f:
+ txt = f.read()
+ # replace vss / vdd : linkage bit with vss/vdd in bit
+ txt = txt.replace("linkage bit", "in bit")
+ # and double-underscores
+ txt = txt.replace("__", "_")
+ # write the file
+ with open(fname, "w") as f:
+ f.write(txt)
+++ /dev/null
-#!/usr/bin/env python3
-"""converts NIOLIB and NSXLIB from VBE into VHDL
-"""
-
-import os
-import sys
-
-# use the chroot to set up
-# https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=coriolis2-chroot;hb=HEAD
-# reason for using the chroot: it's standardised across the ls180 project
-
-VASY_CMD = "schroot -c coriolis -d /tmp -- ~/alliance/install/bin/vasy"
-ALLIANCEBASE = "../alliance-check-toolkit/cells"
-ALLIANCE_LIBS = ['nsxlib', 'niolib']
-
-for libname in ALLIANCE_LIBS:
-
- NSXLIB = "%s/%s" % (ALLIANCEBASE, libname)
-
- os.system("mkdir -p %s" % libname)
-
- for fname in os.listdir(NSXLIB):
- if not fname.endswith(".vbe"):
- continue
- print (fname)
- prefix = fname[:-4] # strip ".vbe"
- os.system("cp %s/%s /tmp" % (NSXLIB, fname))
- os.system("rm -f /tmp/%s.vhd" % (prefix))
- os.system("%s -s -I vbe %s %s" % (VASY_CMD, fname, prefix))
- os.system("cp /tmp/%s.vhd %s" % (prefix, libname))
+++ /dev/null
-#!/usr/bin/env python3
-
-"""builds nsxlib and other VHD files into object files using ghdl
-"""
-
-import os
-import sys
-
-SRC = [('nsxlib', 'vhd'),
- ('niolib', 'vhd'),
- ('vst_src', 'vst')]
-
-# make and change to obj dir
-os.system("mkdir -p obj")
-cwd = os.getcwd()
-os.chdir("obj")
-
-for srcdir, suffix in SRC:
- # run ghdl -a on every vhd / vst file
- for fname in os.listdir("../%s" % srcdir):
- if not fname.endswith(".%s" % suffix):
- continue
- print (fname)
- prefix = fname[:-4] # strip ".vhd"
- os.system("ghdl -a -g --std=08 ../%s/%s" % (srcdir, fname))
-
-# back to original dir
-os.chdir(cwd)
+++ /dev/null
-#!/usr/bin/env python3
-
-"""makes corrections to vst source from coriolis2 P&R
-"""
-
-import os
-import sys
-
-# run through all files
-for fname in os.listdir("vst_src"):
- if not fname.endswith(".vst"):
- continue
- print (fname)
- # read the file
- fname = "vst_src/"+fname
- with open(fname) as f:
- txt = f.read()
- # replace vss / vdd : linkage bit with vss/vdd in bit
- txt = txt.replace("linkage bit", "in bit")
- # and double-underscores
- txt = txt.replace("__", "_")
- # write the file
- with open(fname, "w") as f:
- f.write(txt)
projects / soc-cocotb-sim.git / commitdiff