add ghdl yosys scripts for compiling ls180

diff --git a/small_jtag_test/Makefile b/small_jtag_test/Makefile
index 778623fdb7aad7f87bfeba356543bdae02e6873f..d1b97c2a8a41a6529d493de4206e4d043372966d 100644 (file)
--- a/small_jtag_test/Makefile
+++ b/small_jtag_test/Makefile
@@ -5,6 +5,12 @@ YOSYS_INCLUDE  = $(shell yosys-config --datdir)/include
 all: tb
        ./tb
 
+ls180_ghdl: main.cpp ls180_ghdl.cpp
+       clang++ \
+    -DDESIGN=cxxrtl_design::p_ls180 \
+    -DCXX_FILE=\"ls180_ghdl.cpp\" \
+    -g -O3 -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@
+
 tb_ghdl: main.cpp add_ghdl.cpp
        clang++ \
     -DDESIGN=cxxrtl_design::p_add \

diff --git a/small_jtag_test/add_ghdl.ys b/small_jtag_test/add_ghdl.ys
new file mode 100644 (file)
index 0000000..09e87b1
--- /dev/null
+++ b/small_jtag_test/add_ghdl.ys
@@ -0,0 +1,6 @@
+plugin -i ghdl
+script nsxlib/ghdl.ys
+script niolib/ghdl.ys
+ghdl --std=08 add
+write_cxxrtl add_ghdl.cpp
+write_verilog add_ghdl.v

diff --git a/small_jtag_test/ls180_ghdl.ys b/small_jtag_test/ls180_ghdl.ys
new file mode 100644 (file)
index 0000000..f216e75
--- /dev/null
+++ b/small_jtag_test/ls180_ghdl.ys
@@ -0,0 +1,6 @@
+plugin -i ghdl
+script nsxlib/ghdl.ys
+script niolib/ghdl.ys
+ghdl --std=08 ls180
+write_cxxrtl ls180_ghdl.cpp
+write_verilog ls180_ghdl.v