TLB/src/CacheWalker.py

   1 from nmigen import Memory, Module, Signal
   2 from nmigen.cli import main
   3 from math import log
   4
   5 class CacheWalker():
   6     """ The purpose of this module is to search a memory block given an
   7         associativity.  This module will attempt to find a matching
   8         entry when given an address, and perform permission validation
   9         if successful.
  10     """
  11     def __init__(self, data_size, assoc, mem):
  12         """ Arguments:
  13             * data_size: (bit count) The size of the data words being processed
  14             * assoc: (int) The associativity of the memory to be parsed
  15             * mem: (nmigen.Memory) The memory to be parsed
  16
  17             Return:
  18             1. An entry was found -> Return PTE, set hit HIGH, set valid HIGH
  19             2. An entry was NOT found -> set hit LOW, set valid HIGH
  20             3. A permission fault occurs -> set hit LOW, set valid LOW
  21         """
  22         # Parameter parsing
  23         self.assoc = assoc # Assciativity of the cache
  24
  25         self.read_port = mem.read_port
  26         self.write_port = mem.write_port
  27
  28         if (mem_size % assoc != 0):
  29             print("Cache Walker: Memory cannot be distributed between sets")
  30
  31         self.set_count = mem.depth / assoc # Number of sets in memory
  32         self.set_bit_count = log(set_count, 2) # Bit count for sets
  33         # Ensure set_bit_count is fully represented
  34         if(set_count % 2 != 0):
  35             set_bit_count += 1
  36
  37         self.assoc_bits = Signal(set_bit_count) # Bits for associativity
  38
  39         # Inputs
  40         self.vma = Signal(36) # Virtual Memory Address (VMA)
  41
  42         # Output
  43         self.hit = Signal(1) # Denotes if the VMA had a mapped PTE
  44         self.pte = Signal(64) # PTE that was mapped to by the VMA
  45         self.valid = Signal(1) # Denotes if the permissions are correct